Magnetic RAM array architecture

Patent metadata

Field	Value
Publication number	US-9747968-B2
Application number	US-201615356117-A
Country	US
Kind code	B2
Filing date	Nov 18, 2016
Priority date	Jul 29, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A magnetic random access memory (MRAM) array including: a plurality of MRAM cells arranged in an array configuration, each comprising a first type nTron and a magnetic memory element; a wordline select circuit comprising of a second type nTron to drive a plurality of parallel wordlines; and a plurality of bitline select circuits, each comprising of said second type nTron for writing to and reading from a column of memory cells in the array and each capable of selecting a single MRAM cell for a memory read or write operation, wherein the second nTron has a higher current drive than the first nTron.

First claim

The invention claimed is:

1. A method for writing to and reading from a magnetic random access memory (MRAM) array, each memory cell in the array comprising of a memory cell select nTron (SnT) and a memory element, the method comprising:
selecting a memory cell of the MRAM array by driving a word line and a bit line by a line select nTron (LnT), wherein the LnT has a higher current drive than the SnT;
performing a memory write operation to a single MRAM cell by applying an nTron signal at a gate of the SnT of the single MRAM cell to switch the SnT to a resistive state; and
performing a memory read operation from the single MRAM cell by applying a Single Flux Quantum (SFQ) signal at a gate of the SnT of the single MRAM cell to switch the SnT to a resistive state, applying a current to the memory element smaller than a critical current of the memory element to keep the memory element at its current state while being read, and sensing the voltage at the memory element to determine the resistive state of the memory element.

2. The method of claim 1 , wherein the memory element is a Cryogenic Orthogonal Spin-Transfer (COST) device.

3. The method of claim 2 , wherein the each of the memory cells further comprises an inductance.

4. The method of claim 1 , wherein the memory element is a Cryogenic Spin Hall Effect (CSHE) device.

5. The method of claim 1 , wherein the line select nTron is capable of driving a linear array of 64 memory cell select nTrons for a memory word of 64 bits wide.

6. The method of claim 1 , further comprising reading the state of said each MRAM cell using the determined resistive state of the memory element.

7. The method of claim 1 , further comprising keeping the memory element at its current state while being read by applying a current to the memory element smaller than a critical current of the memory element, during a memory read operation.

Assignees

• Raytheon Bbn Technologies Corp
• Hypres Inc
• Raytheon Bbn Technologies Corp

Inventors

• Ohki Thomas
• Mukhanov Oleg
• Kirichenko Alex

Classifications

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title