Memory device and method with data input

Patent metadata

Field	Value
Publication number	US-11195571-B2
Application number	US-201816136895-A
Country	US
Kind code	B2
Filing date	Sep 20, 2018
Priority date	Nov 28, 2017
Publication date	Dec 7, 2021
Grant date	Dec 7, 2021

Abstract

A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

First claim

What is claimed is:

1. An operation method of a memory device which is configured to receive data from an external device through a plurality of data lines, the method comprising:
generating a first internal code based on a first code and a second code, wherein the first code includes information of a first reference voltage associated with a first data line of the plurality of data lines and the second code includes information about a first decision feedback equalization (DFE) level associated with the first data line;
generating a second internal code based on a third code and a fourth code, wherein the third code includes information of a second reference voltage associated with a second data line of the plurality of data lines and the fourth code includes information about a second decision feedback equalization (DFE) level associated with the second data line;
generating a first reference voltage set and a second reference voltage set based on the first internal code and the second internal code, respectively; and
sampling first input data applied on the first data line based on the first reference voltage set and second input data applied on the second data line based on the second reference voltage set.

2. The operation method of claim 1 , wherein:
the first reference voltage set comprises a first upper reference level voltage equaling a sum of the first reference voltage and the first DFE level, and a first lower reference voltage equaling the first reference voltage minus the first DFE level; and
the second reference voltage set comprises a second upper reference level voltage equaling a sum of the second reference voltage and the second DFE level, and a second lower reference voltage equaling the second reference voltage minus the second DFE level.

3. The operation method of claim 2 , wherein the sampling of the first input data comprises:
concurrently applying the first upper reference voltage and the first lower reference voltage as inputs to a multiplexer;
applying a selection signal to the multiplexer to select the first upper reference voltage or the first lower reference voltage;
outputting the selected one of the first upper reference voltage and the first lower reference voltage to one input of a comparator; and
receiving the first input data at a second input of the comparator, and outputting a comparison result at a sampling point, indicative of a bit value of the first input data at the sampling point.

4. The operation method of claim 1 , wherein the first internal code and the first reference voltage set are generated by a first data line driver circuit associated with the first data line, based on the first and second codes obtained by the first data line driver circuit, and the method further comprising:
grouping at least one further data line driver circuit, associated with at least one further data line, with the first data line driver circuit and obtaining, by the at least one further data line driver circuit, the first and second codes;
wherein the at least one further driver circuit generates the same first reference voltage set as that generated by the first data line driver circuit, based on the first and second internal codes, and determines bit values of further data by sampling the further data using the same first reference voltage set.

5. The operation method of claim 4 , wherein the first and further driver circuits are grouped based on a criterion of physical adjacency therebetween.

6. The operation method of claim 1 , wherein levels of the first and second reference voltages are different from each other, and the first and second DFE levels are different from each other.

7. The operation method of claim 1 , wherein the first to fourth codes are stored in at least one mode register of the memory device.

8. The operation method of claim 7 , wherein each of the first to fourth codes is stored in the at least one mode register in a training operation of the memory device.

9. The operation method of claim 1 , wherein the memory device communicates with an external device, based on a graphic double data rate (GDDR) interface.

10. A memory system comprising:
a plurality of memory devices, each comprising:
a memory cell array; and
a data line driver unit configured to drive the memory cell array and receive first input data via a respective first data line and receive second input data via a respective second data line;
wherein each data line driver unit comprises:
a first data line driver circuit configured to generate a first reference voltage set based on a first code and a second code associated with the first data line, and to determine bit values of the first input data received through the first data line, based on the first reference voltage set, the first code including information of a first reference voltage level associated with the first data line, the second code including information of a first decision feedback equalization (DFE) level associated with the first data line; and
a second data line driver circuit configured to generate a second reference voltage set based on a third and a fourth code associated with the second data line and to determine bit values of the second input data received through the second data line, based on the second reference voltage set, the third code including information of a second reference voltage level associated with the second data line, the fourth code including information of a second DFE level associated with the second data line.

11. The memory system of claim 10 , wherein the first and second reference voltage levels are different from each other, and the first and second DFE levels are different from each other.

12. The memory system of claim 10 , further comprising:
at least one mode register configured to store the first to fourth codes.

13. The memory system of claim 12 , wherein, for each memory device, the first to fourth codes are stored in the at least one mode register in a training operation of the memory device.

14. The memory system of claim 10 , wherein the first data line driver circuit includes a first reference voltage generator configured to generate the first reference voltage set including a first upper reference voltage and a first lower reference voltage that are concurrently output, wherein the first reference voltage generator includes:
an adder circuit that adds the first code and the second code to generate a first sub-code for the first upper reference voltage;
a first decoder circuit configured to decode the first sub-code;
an upper reference voltage selector circuit configured to output the first upper reference voltage, based on the decoding result of the first decoder circuit;
a subtractor circuit that performs a subtraction operation on the first code and the second code to generate a second sub-code for the first lower reference voltage;
a second decoder circuit configured to decode the second sub-code; and
a lower reference voltage selector circuit configured to output the first lower reference voltage, based on the decoding result of the second decoder.

15. The memory system of claim 14 , wherein each data line driver unit further comprises a resistive ladder coupled to each of the upper reference voltage selector circuit and the lower reference voltage selector circuit, wherein the resistive ladder concurrently provides the upper and lower reference voltages.

16. The memory system of claim 10 , wherein each data line driver unit further comprises at least one third data line driver circuit, associated with at least one third data line that receives

Assignees

• Samsung Electronics Co Ltd

Inventors

• Eom Yoon-Joo
• Bae Seungjun
• Kwon Hye Jung
• Kim Young-Ju

Classifications

• G11C29/021

  in voltage or current generators · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title