Memory controllers, systems, and methods supporting multiple request modes

Patent metadata

Field	Value
Publication number	US-9378787-B2
Application number	US-201414305799-A
Country	US
Kind code	B2
Filing date	Jun 16, 2014
Priority date	Apr 12, 2007
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

First claim

What is claimed is:

1. A memory controller to direct requests to sections of a memory die, via respective channels, the memory controller comprising:
for each one of the respective channels, at least one queue to schedule issuance of respective ones of the requests to a corresponding one of the sections of the memory die;
logic to receive the requests from a host and to steer each request to the at least one queue for one of the respective channels according to a corresponding one of the sections of the memory die to be accessed according to the request; and
for each one of the respective channels, interface circuitry to transmit requests from the at least one queue to the corresponding one of the sections, via the one of the respective channels;
wherein each section of the memory die includes banks, and wherein
the memory controller is to transmit requests to each bank of the memory die no more frequently than once during a first interval of time,
the logic is to steer each request to a corresponding bank in the corresponding one of the sections of the memory die, and
the interface circuitry for each one of the respective channels is to transmit the respective ones of the requests from the at least one queue via the one of the respective channels in a manner threaded between banks of the corresponding one of the sections of the memory die, at a rate that is greater than once per first interval of time.

2. The memory controller of claim 1 , wherein:
the memory controller is to couple to the memory die via each one of the respective channels via at least one corresponding link;
the memory controller is to receive each of the requests from the host in a form having deserialized command and address information; and
the interface circuitry for each one of the respective channels is to transmit requests to the memory die over the respective one of the channels in a manner such that corresponding command and address information is at least partially serialized over each link of the at least one corresponding link of the respective one of the channels.

3. The memory controller of claim 2 , wherein:
the at least one corresponding link of each respective one of the channels includes at least eight dedicated data links and at least one dedicated request link; and
the memory controller is to exchange data over each link of the at least eight dedicated data links of each respective one of the channels at a first data rate; and
the memory controller is to serially exchange request information over each link of the at least one dedicated request link of each respective one of the channels at a second data rate that is no less than half of the first data rate.

4. The memory controller of claim 1 , wherein the memory controller is to direct the requests to at least four respective sections of the memory die, via at least four respective channels, and is to exchange data in accordance with each request that is no less than one byte in granularity.

5. The memory controller of claim 4 , wherein:
the memory controller has at least two operational modes, including
a first mode in which the memory controller is to direct respective ones of the requests to the memory die via exactly two respective channels, and is to exchange data in accordance with each request that is no less than one byte in granularity, and
a second mode in which the memory controller is to direct respective ones of the requests to the memory die, via exactly four respective channels, and is to exchange data in accordance with each request that is no less than one byte in granularity; and

the memory controller is to configure the logic to steer each request according to whether the memory controller is to operate in the first mode or the second mode, such that the logic is to direct respective ones of the requests to one of the exactly two respective channels in the first mode and is to direct respective ones of the requests to one of the exactly four respective channels in the second mode.

6. The memory controller of claim 5 , wherein the memory controller further comprises a register to store a value indicating a particular mode of the at least two operational modes, and logic to cause the memory controller to operate in one of the first mode or the second mode according to the value stored in the register.

7. The memory controller of claim 1 , embodied as a dynamic random access memory (DRAM) controller, wherein the memory die is a DRAM memory die and wherein the threaded requests each comprise an activate command and a column access command that are to be transmitted at respective times.

8. The memory controller of claim 1 , wherein the memory controller has at least two operational modes, including:
a first mode in which
the logic is to receive the requests from the host and to steer each request to the at least one queue for the one of the respective channels according to the corresponding one of the sections of the memory die to be accessed according to the request, and
the interface circuitry for each one of the respective channels is to transmit the respective ones of the requests from the at least one queue to the corresponding one of the sections, via the one of the respective channels; and

a second mode in which
the logic is to steer all requests to each one of the respective channels,
the interface circuitry for each one of the respective channels is to transmit all requests to the memory die, via the respective channel, and
each of the sections of the memory die is to exchange a slice of data with the memory controller in association with each request.

9. A dynamic random access memory (DRAM) controller to direct requests to first and second sections of a DRAM die, via respective first and second channels, the DRAM controller comprising:
at least one first queue to schedule issuance of first ones of the requests to the first section of the DRAM die;
at least one second queue to schedule issuance of second ones of the requests to the second section of the DRAM die;
logic to receive the requests from a host and to steer each one of the requests request to one of the at least one first queue or the at least one second queue according to the section of memory to be accessed by the one of the requests;
first interface circuitry to transmit the first ones of the requests from the at least one first queue to the first section via the first channel; and
second interface circuitry to transmit the second ones of the requests from the at least one second queue to the first section via the second channel;
wherein each section of the first section and the second section of the memory die includes banks, and wherein
the DRAM controller is to transmit requests to each bank of the memory die no more frequently than once during a first interval of time,
the logic is to steer each request to a corresponding bank in the corresponding one of the sections of the memory die, and
the interface circuitry for each of the first channel and the second channel is to transmit the respective ones of the requests from the at least one queue via the respective first or second channel in a manner threaded between banks of the corresponding section of the memory die, at a rate that is greater than once per first interval of time.

10. The DRAM controller of claim 9 , wherein:
the DRAM controller is to couple to the memory die via each one of the first channel and the second channel, each via at least one corresponding link;
the DRAM controller is to receive each of the requests from the host in a form having deserialized command and address information; and
the first interface circuitry and the second interface circuitry are each to transmit

Assignees

• Rambus Inc

Inventors

• Perego Richard E
• Ware Frederick A

Classifications

• G06F13/1694

  Configuration of memory controller to different memory types · CPC title

• G06F13/1678 Primary

  using bus width · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C7/1075 Primary

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title

• G06F13/1684

  using multiple buses · CPC title