Compressed test patterns for a field programmable gate array

Patent metadata

Field	Value
Publication number	US-11193975-B2
Application number	US-201816024722-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Dec 7, 2021
Grant date	Dec 7, 2021

Abstract

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

First claim

What is claimed is:

1. A method to compress a test pattern onto a field programmable gate array (FPGA) to test a device under test (DUT), the method comprising:
identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles;
identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles;
analyzing the identified values;
compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins; and
storing the compressed values on the FPGA.

2. The method of claim 1 , wherein a value for a drive pin is a selected one of 0 or 1; and wherein a value for a compare pin is a selected one of 0, 1, or X.

3. The method of claim 1 , wherein compressing further includes identifying a plurality of values of drive pins and compare pins for an identified test cycle.

4. The method of claim 1 , wherein compressing further includes identifying, based on the analysis, a subset of drive pins and/or compare pins having respective values for N subsequent test cycles after an identified test cycle that are equal to respective values of the subset of drive pins and/or compare pins of a first test cycle.

5. The method of claim 4 , wherein compressing further includes:
creating, based upon the analysis, a compressed page (CP) to store at least a portion of the subset of drive pins and/or compare pins and their respective values; and
creating, based upon the analysis, a call header (CH) page associated with the CP, wherein the CH page includes an indication of one or more of:
a memory address of the CP,
a number of tester cycles to be generated from data in the CP,
a memory map within the associated CP of per-pin data, and
a configuration for each pin of the plurality of pins.

6. The method of claim 5 , wherein the configuration for each pin includes a pin mode indication of a selected one of: “no data”, “1 bit”, “2 bits”, or “4 bits”.

7. The method of claim 6 , further comprising, upon the pin mode indication of “no data” for a pin, a value for the pin is in the CH page and the pin data value is to remain constant for the number of tester cycles.

8. The method of claim 7 , further comprising:
upon the pin mode indication of “1 bit” for a pin, identifying a value for the pin to be one of two possible values;
upon the pin mode indication of “2 bit” for the pin, identifying a value for the pin to be one of four possible values; and
upon the pin mode indication of “4 bit” for the pin, identifying a value for the pin to be one of 16 possible values.

9. The method of claim 5 , wherein the CH page further includes a pin location offset in the associated CP to indicate a first field beginning at the location offset, wherein the first field is to indicate a selected one of a command field or a data field.

10. The method of claim 9 , wherein a command field further includes a command indicator and command data; and wherein the command indicator is to indicate a repeating of a prior state of the pin for the number of tester cycles indicated by the command data.

11. A non-transitory computer readable medium that includes instructions, when executed on a processor, to cause the processor to:
identify values of a plurality of drive pins for a plurality of test cycles to apply to an input of a DUT for each of the plurality of test cycles;
identify values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles;
analyze the identified values;
compress, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins; and
store the compressed values on the FPGA.

12. The non-transitory computer readable medium of claim 11 , wherein to compress further includes to identify a plurality of values of drive pins and compare pins for an identified test cycle.

13. The non-transitory computer readable medium of claim 11 , wherein to compress further includes to identify, based on the analysis, a subset of drive pins and/or compare pins having respective values for N subsequent test cycles after an identified test cycle that are equal to respective values of the subset of drive pins and/or compare pins of a first test cycle.

14. The non-transitory computer readable medium of claim 13 , wherein to compress further includes to:
create, based upon the analysis, a compressed page (CP) to store at least a portion of the subset of drive pins and/or compare pins and their respective values; and
create, based upon the analysis, a call header (CH) page associated with the CP, wherein the CH page includes an indication of one or more of:
a memory address of the CP,
a number of tester cycles to be generated from data in the CP,
a memory map within the associated CP of per-pin data, and
a configuration for each pin of the plurality of pins.

15. The non-transitory computer readable medium of claim 14 , wherein the configuration for each pin includes a pin mode indication of a selected one of: “no data”, “1 bit”, “2 bits”, or “4 bits.”

16. An apparatus comprising:
means for identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of a device under test (DUT) for each of the plurality of test cycles;
means for identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles;
means for analyzing the identified values;
means for compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins; and
means for storing the compressed values on the field programmable gate array (FPGA).

17. The apparatus of claim 16 , wherein a value for a drive pin is a selected one of 0 or 1; and wherein a value for a compare pin is a selected one of 0, 1, or X.

18. The apparatus of claim 16 , wherein means for compressing further includes means for identifying a plurality of values of drive pins and compare pins for an identified test cycle.

19. The apparatus of claim 16 , wherein means for compressing further includes: means for identifying, based on the analysis, a subset of drive pins and/or compare pins having respective values for N subsequent test cycles after an identified test cycle that are equal to respective values of the subset of drive pins and/or compare pins of a first test cycle.

20. The apparatus of claim 19 , wherein means for compressing further includes:
means for creating, based upon the analysis, a compressed page (CP) to store at least a portion of the subset of drive pins and/or compare pins and their respective values; and
means for creating, based upon the analysis, a call header (CH) page associated with the CP, wherein the CH page includes an indication of one or more of:
a memory address of the CP,
a number of tester cycles to be generated from data in the CP,
a memory map within the associated CP of per-pin data, and
a configuration for each pin of the plurality of pins.

Assignees

• Intel Corp
• Intel Corportion

Inventors

• Nelson Christopher J
• Rollins Shelby G
• Tilala Hiren V
• Hendricks Matthew
• Pathy Sundar V
• Callahan Timothy J
• Pager Jared
• Neeb James
• Inman Bradly
• Sturges Stephen

Classifications

• G01R31/318335 Primary

  Test pattern compression or decompression (compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921) · CPC title

• G01R31/316

  Testing of analog circuits {(G01R31/2851 takes precedence)} · CPC title

• G01R31/318519

  Test of field programmable gate arrays [FPGA] · CPC title

• G01R31/318547

  Data generators or compressors · CPC title

• G01R31/31703

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title