Compressed test patterns for a field programmable gate array
US-11193975-B2 · Dec 7, 2021 · US
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Pager Jared patents
Pager Jared is listed as an inventor on 2 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Pager Jared |
| Total patents | 2 |
| First publication | Jan 2, 2020 |
| Latest publication | Dec 7, 2021 |
Notable patents
Publications ranked by popularity score, then publication date.
Compressed test patterns for a field programmable gate array
US-2020003836-A1 · Jan 2, 2020 · US
Recent patents
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 2 |
| Intel Corportion | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G01R31/318335 | 2 |
| G01R31/316 | 2 |
| G01R31/318519 | 2 |
| G01R31/318547 | 2 |
| G01R31/31703 | 2 |