Selective recess of interconnects for probing hybrid bond devices

Patent metadata

Field	Value
Publication number	US-11189585-B2
Application number	US-201916703298-A
Country	US
Kind code	B2
Filing date	Dec 4, 2019
Priority date	Dec 4, 2019
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.

First claim

We claim:

1. An Integrated Circuit (IC) device, comprising:
a first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric; and
a second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric, wherein a first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components,
wherein a second of the first interconnect structures is set back a distance from a plane of the bond interface, and wherein a void is between a free surface of the second of the first interconnect structures and an opposing free surface of either the second dielectric or the second of the second interconnect structures.

2. The IC device of claim 1 , wherein the free surface of the second of the first interconnect structures has more surface topography than opposing surface of either the second dielectric or a second of the second interconnect structures.

3. The IC device of claim 2 , wherein the free surface of the second of the first interconnect structures has a z-height variation of at least lum.

4. The IC device of claim 1 , wherein the second of the first interconnect structures is set back a first distance from an opposing surface the second of the second interconnect structures, and wherein the second of the first interconnect structures is set back from the plane of the bond interface by a second distance, greater than the first distance.

5. The IC device of claim 4 , wherein a surface of the second of the first interconnect structures is dished away from the plane of the bond interface.

6. The IC device of claim 5 , wherein a surface of a second of the second interconnect structures is also dished away from the plane of the bond interface.

7. The IC device of claim 1 , wherein the distance is at least 2 um.

8. The IC device of claim 1 , wherein the first of the first interconnect structures has a first lateral width and the second of the first interconnect structures has a second lateral width that is greater than the first lateral width.

9. The IC device of claim 8 , wherein the difference between the first lateral width and the second lateral width is at least 5 microns.

10. The IC device of claim 1 , wherein the first dielectric is between sidewalls of the first interconnect structures.

11. The IC device of claim 10 , wherein the distance between the first sidewall and the second sidewall is at least 500 nanometers.

12. A system, comprising:
a microprocessor; and
a memory coupled to the microprocessor, wherein at least one of the memory or the microprocessor comprises: a first integrated circuit (IC) die comprising a first dielectric and a plurality of adjacent first interconnect structures; and
a second IC die comprising a second dielectric and a plurality of adjacent second interconnect structures, wherein a first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second IC die, and wherein a second of the first interconnect structures is set back a distance from a plane of the bond interface, and wherein a void is between a free surface of the second of the first interconnect structures and an opposing free surface of either the second dielectric or the second of the second interconnect structures.

13. The system of claim 12 , wherein the microprocessor comprises the first IC die and wherein the memory comprises the second IC die.

14. The system of claim 12 , wherein the at least one of the first or second IC die is coupled to a printed circuit board.

15. A method for making an IC device, comprising:
forming a plurality of adjacent first interconnect structures within a first dielectric of a first component;
recessing a first of the first interconnect structures below a surface of the first dielectric that is planar with a second of the first interconnect structures; and
bonding the first component to a second component wherein the second component comprises a plurality of second interconnect structures within a second dielectric, and wherein a bond interface is formed between the second of the first interconnect structures and a first of the second interconnect structures, and wherein the first of the first interconnect structures is set back from the plane of the bond interface, and wherein a void is between a free surface of the first of the first interconnect structures and an opposing free surface of either the second dielectric or a second of the second interconnect structures.

16. The method of claim 15 , wherein recessing the first of the first interconnect structures below the surface of the first dielectric comprises:
polishing the surface of the first dielectric, wherein the plurality of first interconnect structures is polished to be substantially planar with the surface of the first dielectric;
forming an etch mask over the surface of the first dielectric, wherein an aperture is over the first of the first interconnect structures; and
etching back the first of the first interconnect structures so that a free surface of the first of the first interconnect structures is below the surface of the first dielectric.

17. The method of claim 15 , wherein forming a plurality of first interconnect structures in a surface of a first dielectric of a first component comprises forming the second of the first interconnect structures having a first width and the first of the plurality of first interconnect structures having a second width that is greater than the first width.

Assignees

• Intel Corp

Inventors

• Mueller Brennen K
• Elsherbini Adel
• Kobrinsky Mauro
• Swan Johanna
• Liff Shawna
• Tadayon Pooya

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title