Capacitive coupling in a direct-bonded interface for microelectronic devices

Patent metadata

Field	Value
Publication number	US-10811388-B2
Application number	US-201816212248-A
Country	US
Kind code	B2
Filing date	Dec 6, 2018
Priority date	Sep 28, 2015
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

First claim

The invention claimed is:

1. A microelectronic device, comprising:
a dielectric-to-dielectric direct bond between a first die and a second die, the first die and the second die being direct-bonded together at a bonding interface;
a metal-to-metal direct bond at the bonding interface forming a conductive interconnect between the first die and the second die;
a capacitive interconnect between the first die and the second die formed at the bonding interface, the capacitive interconnect comprising a first layer of a first dielectric medium on a first metal of the first die, a second layer of a second dielectric medium on a second metal of the second die, and a layer of a polymer between the first layer and the second layer; and
wherein a combined thickness of the first layer, the second layer, and the layer of the polymer is in a range of 25-50 nanometers.

2. The microelectronic device of claim 1 , wherein the first die and the second die are direct-bonded together at the bonding interface with a dielectric-to-dielectric direct bond between respective nonmetal surfaces of the first die and the second die.

3. The microelectronic device of claim 2 , wherein the dielectric-to-dielectric direct bond between the first die and the second die creates a capacitive coupling of the capacitive interconnect.

4. The microelectronic device of claim 1 , wherein the first metal of the capacitive interconnect in the first die is recessed from the bonding interface and the second metal of the capacitive interconnect in the second die is flush with the bonding interface.

5. The microelectronic device of claim 1 , wherein the first metal of the capacitive interconnect in the first die is recessed from the bonding interface and the second metal of the capacitive interconnect in the second die is also recessed from the bonding interface.

6. The microelectronic device of claim 1 , wherein the first dielectric medium of the capacitive interconnect or the second dielectric medium of the capacitive interconnect comprises silicon dioxide, silicon nitride, air, or a high dielectric material.

7. The microelectronic device of claim 1 , wherein the first dielectric medium of the capacitive interconnect, the second dielectric medium of the capacitive interconnect, and the layer of the polymer comprise asymmetrical thicknesses with respect to a horizontal plane of the bonding interface between the first die and the second die.

8. The microelectronic device of claim 1 , wherein a spacing distance between the first metal in the first die and the second metal in the second die is selected to provide a capacitance value for the capacitive interconnect.

9. The microelectronic device of claim 1 , wherein a thickness and a dielectric constant of the layer of the polymer determines a capacitance of the capacitive interconnect.

10. The microelectronic device of claim 1 , wherein the conductive interconnect comprises a direct-bonded power interconnect or a direct-bonded ground interconnect.

11. The microelectronic device of claim 1 , wherein the capacitive interconnect comprises a signal line between the first die and the second die.

12. The microelectronic device of claim 1 , further comprising a conductive through-via created by a via-last fabrication process penetrating at least part way into the first die or penetrating at least part way into both the first die and the second die.

13. The microelectronic device of claim 1 , wherein at least the first layer or the second layer is direct-bonded to the layer of the polymer.

14. The microelectronic device of claim 1 , wherein the first metal of the first die and the second metal of the second die comprise a single capacitive signal line across the bonding interface, and the first ultrathin layer of the first dielectric medium, the second layer of the second dielectric medium, and the layer of the polymer are disposed at the bonding interface only between the first metal of the first die and the second metal of the second die.

15. A process, comprising:
creating a first direct bond between respective dielectric surfaces at a bonding interface of two dies;
creating a second direct bond between respective conductive interconnects at the bonding interface of the two dies; and
creating a capacitive coupling at the bonding interface for a capacitive interconnect between the two dies;
the capacitive interconnect comprising a first layer of a first dielectric medium on a first metal of a first die of the two dies, a second layer of a second dielectric medium on a second metal of a second die of the two dies, and a layer of a polymer between the first layer and the second layer; and
wherein a combined thickness of the first ultrathin layer, the second layer, and the layer of the polymer is in a range of 25-50 nanometers.

16. The process of claim 15 , wherein creating the second direct bond between respective conductive interconnects at the bonding interface and creating the capacitive coupling at the bonding interface result from the same direct bonding process at the same bonding interface.

17. The process of claim 15 , wherein the direct bond between the dielectric surfaces comprises an oxide-to-oxide direct bond; and
wherein the direct bond between the respective conductive interconnects comprises a metal-to-metal direct bond.

Assignees

• Invensas Corp

Inventors

• Haba Belgacem
• Sitaram Arkalgud R

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10W99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title