Microstructure modulation for 3D bonded semiconductor structure with an embedded capacitor

Patent metadata

Field	Value
Publication number	US-10141392-B2
Application number	US-201715440857-A
Country	US
Kind code	B2
Filing date	Feb 23, 2017
Priority date	Feb 23, 2017
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic capacitor plate structure embedded therein, wherein each metallic capacitor plate structure has a columnar grain microstructure. A high-k dielectric material is present between the first and second metallic capacitor plate structures. The presence of the columnar grain microstructure in the metallic capacitor plate structures can provide an embedded capacitor that has an improved quality factor, Q.

First claim

What is claimed is:

1. A three-dimensional (3D) bonded semiconductor structure comprising:
a first semiconductor structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and a first metallic capacitor plate structure having a columnar grain microstructure embedded in the first bonding oxide layer; and
a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and a second metallic capacitor plate structure having a columnar grain microstructure embedded in the second bonding oxide layer, wherein a high-k dielectric material is present between the first metallic capacitor plate structure and the second metallic capacitor plate structure, and wherein a bonding interface is present between the first and second bonding oxide layers and another bonding interface is present between the high-k dielectric material and the first metallic capacitor plate structure or the second metallic capacitor plate structure.

2. The 3D bonded semiconductor structure of claim 1 , further comprising a first dummy metallic pad structure embedded in the first bonding oxide layer and a second dummy metallic pad structure embedded in the second bonding oxide layer, wherein a yet other bonding interface is present between the first dummy metallic pad structure and the second dummy metallic pad structure.

3. The 3D bonded semiconductor structure of claim 2 , wherein the first and second dummy metallic pad structures have a columnar grain microstructure, and wherein at least one columnar grain extends across the yet other bonding interface.

4. The 3D bonded semiconductor structure of claim 3 , wherein the first and second metallic capacitor plate structures and the first and second dummy metallic pad structures are composed of a same metal or metal alloy.

5. The 3D bonded semiconductor structure of claim 4 , wherein the metal or metal alloy comprises tantalum, tungsten, cobalt, rhodium, ruthenium, aluminum, copper or alloys thereof.

6. The 3D bonded semiconductor structure of claim 1 , wherein the high-k dielectric material comprises HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO X N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , SiON, SiN X , a silicate thereof, or an alloy thereof, wherein each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.

7. The 3D bonded semiconductor structure of claim 1 , wherein each of the first and second interconnect structures comprises at least one interconnect dielectric material and one or more interconnect metallic structures embedded therein.

8. The 3D bonded semiconductor structure of claim 7 , wherein the at least one or more interconnect metallic structures are composed of copper, a copper-aluminum alloy, a copper manganese alloy, aluminum or an aluminum-copper alloy.

9. The 3D bonded semiconductor structure of claim 1 , wherein the high-k dielectric material is present on a recessed surface of the first metallic plate capacitor structure or the second metallic plate capacitor structure.

10. The 3D bonded semiconductor structure of claim 1 , wherein the high-k dielectric material has outermost edges that are vertically aligned to the outermost edges of the first and second metallic capacitor plate structures.

11. A method of forming a three-dimensional (3D) bonded semiconductor structure, the method comprising:
providing a first semiconductor structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and a first metallic capacitor plate structure having a columnar grain microstructure embedded in the first bonding oxide layer, and a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and a second metallic capacitor plate structure having a columnar grain microstructure embedded in the second bonding oxide layer;
forming a high-k dielectric material on a surface of the first metallic capacitor plate structure or the second metallic capacitor plate structure; and
bonding the first semiconductor structure to the second semiconductor structure, wherein the bonding provides a bonding interface between the first and second bonding oxide layers and another bonding interface between the high-k dielectric material and the first metallic capacitor plate structure or the second metallic capacitor plate structure.

12. The method of claim 11 , further comprising a first dummy metallic pad structure embedded in the first bonding oxide layer, and a second dummy metallic pad structure embedded in the second bonding oxide layer, wherein the bonding provides a yet other bonding interface between the first dummy metallic pad structure and the second dummy metallic pad structure.

13. The method of claim 12 , wherein the first and second dummy metallic pad structures have a columnar grain microstructure, and wherein grain growth is initiated during the bonding such that at least one columnar grain extends across the yet other bonding interface.

14. The method of claim 13 , wherein the first and second metallic capacitor plate structures and the first and second dummy metallic pad structures are composed of a same metal or metal alloy.

15. The method of claim 14 , wherein the metal or metal alloy comprises tantalum, tungsten, cobalt, rhodium, ruthenium, aluminum, copper or alloys thereof.

16. The method of claim 11 , wherein said at least one first metallic capacitor plate structure is formed by:
providing a first capacitor plate opening in the first bonding oxide layer;
forming a first metallic layer having a polycrystalline microstructure within the first capacitor plate opening and atop the first bonding oxide layer;
forming a first stress control layer on the first metallic layer;
performing an anneal to convert the polycrystalline microstructure of the first metallic layer into the columnar grain microstructure; and
performing a material removal process, and said at least one second metallic capacitor plate structure is formed by:
providing a second capacitor plate opening in the second bonding oxide layer;
forming a second metallic layer having a polycrystalline microstructure within the second capacitor plate opening and atop the second bonding oxide layer;
forming a second stress control layer on the second metallic layer;
performing an anneal to convert the polycrystalline microstructure of the second metallic layer into the columnar grain microstructure; and
performing a material removal process.

17. The method of claim 16 , wherein each of the first and second stress control layers is composed of tantalum, tantalum nitride, titanium, titanium nitride, cobalt, cobalt nitride, tungsten, tungsten nitride, ruthenium, ruthenium nitride, aluminum or aluminum nitride.

18. The method of claim 16 , wherein the annealing that converts said polycrystalline microstructure to the columnar grain microstructure is performed at a temperature from 100° C. to 800° C.

19. The method of claim 11 , wherein the bonding comprises:
performing wafer to wafer alignment;
bringing the first semiconductor structure into intimate contact with the second semiconductor structure; and
annealing at a temperature from 100° C. to 700° C. and in ambient including at least one of nitrogen, hydrogen, and helium.

20. The method of claim 11 , wherein the formin

Assignees

• IBM

Inventors

• Yang Chih-Chao

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10P90/1914

  using bonding · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title