Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11183497-B2
Application number	US-201916531327-A
Country	US
Kind code	B2
Filing date	Aug 5, 2019
Priority date	Jan 25, 2019
Publication date	Nov 23, 2021
Grant date	Nov 23, 2021

Abstract

A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
first group active fins, on a first region of a substrate, spaced apart from each other in a second direction, each of the first group active fins extending in a first direction, the first and second directions being different from each other, and the substrate including the first region and a second region; and
a first diffusion prevention pattern on the first region of the substrate extending in the second direction through the first group active fins, wherein
the first group active fins include first and second active fins,
the first diffusion prevention pattern extends through a central portion of the first active fin in the first direction dividing the first active fin into a first portion and a second portion, and extends through and contacts an end of the second active fin in the first direction, and
the first portion of the first active fin, the first diffusion prevention pattern, and the second portion of the first active fin are connected with each other to be continuous in the first direction.

2. The semiconductor device of claim 1 , wherein the first group active fins include a plurality of second active fins spaced apart from each other in the second direction, and
wherein the first diffusion prevention pattern extends through and contacts an end of each of the plurality of second active fins in the first direction.

3. The semiconductor device of claim 2 , further comprising an insulation pattern at an opposite side to one of the plurality of second active fins adjacent the first active fin with respect to the first diffusion prevention pattern.

4. The semiconductor device of claim 1 , further comprising a second diffusion prevention pattern extending through a central portion of the first active fin dividing the first active fin and through a central portion of the second active fin dividing the second active fin.

5. The semiconductor device of claim 1 , further comprising:
second group active fins, on the second region of the substrate, spaced apart from each other in the second direction and extending in the first direction; and
a second diffusion prevention pattern on the second region of the substrate extending in the second direction through the second group active fins,
wherein the second group active fins include third and fourth active fins, and
wherein the second diffusion prevention pattern extends through a central portion of the third active fin in the first direction, and extends through an end of the fourth active fin in the first direction.

6. The semiconductor device of claim 5 , wherein the first diffusion prevention pattern extends to the second region of the substrate in the second direction, contacting a sidewall of the second diffusion prevention pattern.

7. The semiconductor device of claim 6 , further comprising a third diffusion prevention pattern, wherein,
the third diffusion prevention pattern is spaced apart from the first diffusion prevention pattern in the first direction, and
the third diffusion prevention pattern,
extends through a central portion of the first active fin dividing the first active fin and extends through a central portion of the second active fin dividing the second active fin on the first region of the substrate, and
extends through a central portion of the third active fin in the first direction dividing the third active fin and extends through an end of the fourth active fin to contact another sidewall of the second diffusion prevention pattern on the second region of the substrate.

8. The semiconductor device of claim 5 , wherein a bottom of the first diffusion prevention pattern is closer to the substrate than a bottom of the second diffusion prevention pattern in a third direction, the third direction being substantially perpendicular to a surface of the substrate.

9. The semiconductor device of claim 5 , wherein the first diffusion prevention pattern includes a nitride, and the second diffusion prevention pattern includes an oxide.

10. The semiconductor device of claim 5 , further comprising:
gate structures spaced apart from each other in the first direction, extending in the second direction on the first and second group active fins; and
source/drain layers on portions of the first and second group active fins adjacent the gate structures,
wherein the first diffusion prevention pattern is between the gate structures.

11. The semiconductor device of claim 1 , wherein,
the first region of the substrate is an NMOS region, and the second region of the substrate is an PMOS region, and
the first and second regions are disposed in the second direction.

12. A semiconductor device, comprising:
an active region on a substrate extending in a first direction and including a first portion, a second portion and a third portion, the first portion having a first width in a second direction substantially perpendicular to the first direction, the second portion having a second width in the second direction less than the first width, and the third portion being between the first and second portions and having a third width in the second direction less than the first width and more than the second width;
a first active fin on the first to third portions of the active region extending in the first direction to a first length;
a second active fin on the first portion of the active region extending in the first direction to a second length less than the first length; and
a first diffusion prevention pattern on the substrate extending in the second direction through the first and second active fins,
wherein the first diffusion prevention pattern extends through a central portion of the active fin in the first direction dividing the first active fin into a first portion and a second portion, and extends through and contacts an end of the second active fin in the first direction,
wherein the first portion of the first active fine, the first diffusion prevention pattern, and the second portion of the first active fin are connected with each other to be continuous in the first direction, and
wherein a distance in the second direction from a sidewall of the third portion of the active region to the first active fin is greater than a distance in the second direction from a sidewall of each of the first and second portions of the active region to the first active fin.

13. The semiconductor device of claim 12 , further comprising an insulation pattern on the third portion of the active region, the insulation pattern being spaced apart from the first active fin.

14. The semiconductor device of claim 12 , further comprising a plurality of third active fins, substantially similar to the second active fin, on the active region.

15. The semiconductor device of claim 12 , wherein a bottom of the first diffusion prevention pattern is closer to the substrate than a bottom of the active region in a third direction, the third direction being substantially perpendicular to a surface of the substrate.

16. The semiconductor device of claim 12 , further comprising a second diffusion prevention pattern spaced apart from the first diffusion prevention pattern in the first direction,
wherein the second diffusion prevention pattern extends through a central portion of the first active fin dividing the first active fin and extends through a central portion of the second active fin dividing the second active fin.

17. A semiconductor device, comprising:
first group active fins on a first region of a substrate spaced apart from each other in a second direction, each of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jae-Boong
• Park Jae-Ho
• Baek Sang-Hoon
• Yu Ji-Su
• Lee Seung-Young
• Jung Jong-Hoon

Classifications

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0193 Primary

  the components including FinFETs · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D62/114

  PN junction isolations · CPC title