Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure

Patent metadata

Field	Value
Publication number	US-11182138-B2
Application number	US-202016808007-A
Country	US
Kind code	B2
Filing date	Mar 3, 2020
Priority date	Apr 23, 2015
Publication date	Nov 23, 2021
Grant date	Nov 23, 2021

Abstract

A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.

First claim

What is claimed is:

1. A computer-implemented method comprising:
receiving, by a compiler, first instructions of a first instruction set, wherein the first instructions define an image processing algorithm and comprise an instruction specifying, using a two-dimensional address comprising an x-coordinate and a y-coordinate, a position of data within a two-dimensional region of image data; and
translating, by the compiler, the first instructions into one or more second instructions of a second instruction set, wherein the second instruction set includes one or more shift instructions that are executable by an image processor comprising an array of execution lanes, wherein the second instructions are operable to cause the image processor to load, into a respective execution lane, the data within the two-dimensional region of image data at the position specified by the two-dimensional address using the one or more shift instructions,
wherein the one or more shift instructions when executed cause the two-dimensional region of image data to be shifted within a two-dimensional shift-register array of the image processor relative to the array of execution lanes.

2. The method of claim 1 , wherein the method further comprises:
causing the image processor to load the data specified by the two-dimensional address into a shift register of the two-dimensional shift-register array, and
causing the image processor to perform the image processing algorithm on the loaded data.

3. The method of claim 1 , wherein the two-dimensional region of image data is a line group of a plurality of line groups of image data for an image frame, and wherein the x-coordinate and the y-coordinate are offsets representing the position of data relative to image data in the line group.

4. The method of claim 3 , wherein each line group in the plurality of line groups is referenced in the first instructions according to a respective unique identifier.

5. The method of claim 3 ,
wherein each line group defines a plurality of image channels, and
wherein the instruction specifying the position of data comprises an identifier for a channel of one of a plurality of channels for the line group.

6. The method of claim 1 , wherein the one or more shift instructions when executed cause the image processor to shift data at the position within the two-dimensional region of image data specified by the two-dimensional address into a shift register of the two-dimensional shift-register array.

7. The method of claim 1 , wherein the translating comprises arranging the shift instructions in an order that minimizes the total number of shift instructions required to execute the image processing algorithm.

8. The method of claim 1 , wherein the first instructions are executable by a virtual processor that is part of a simulation environment for simulating performing the image processing algorithm by the image processor on the data specified by the two-dimensional address.

9. A system comprising one or more computers and one or more storage devices storing instructions that operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
receiving, by a compiler, first instructions of a first instruction set, wherein the first instructions define an image processing algorithm and comprise an instruction specifying, using a two-dimensional address comprising an x-coordinate and a y-coordinate, a position of data within a two-dimensional region of image data; and
translating, by the compiler, the first instructions into one or more second instructions of a second instruction set, wherein the second instruction set includes one or more shift instructions that are executable by an image processor comprising an array of execution lanes, wherein the second instructions are operable to cause the image processor to load, into a respective execution lane, the data within the two-dimensional region of image data at the position specified by the two-dimensional address using the one or more shift instructions,
wherein the one or more shift instructions when executed cause the two-dimensional region of image data to be shifted within a two-dimensional shift-register array of the image processor relative to the array of execution lanes.

10. The system of claim 9 , wherein the operations further comprise:
causing the image processor to load the data specified by the two-dimensional address into a shift register of the two-dimensional shift-register array, and
causing the image processor to perform the image processing algorithm on the loaded data.

11. The system of claim 9 , wherein the two-dimensional region of image data is a line group of a plurality of line groups of image data for an image frame, and wherein the x-coordinate and the y-coordinate are offsets representing the position of data relative to image data in the line group.

12. The system of claim 11 , wherein each line group in the plurality of line groups is referenced in the first instructions according to a respective unique identifier.

13. The system of claim 11 ,
wherein each line group defines a plurality of image channels, and
wherein the instruction specifying the position of data comprises an identifier for a channel of one of a plurality of channels for the line group.

14. The system of claim 9 , wherein the one or more shift instructions when executed cause the image processor to shift data at the position within the two-dimensional region of image data specified by the two-dimensional address into a shift register of the two-dimensional shift-register array.

15. The system of claim 9 , wherein the translating comprises arranging the shift instructions in an order that minimizes the total number of shift instructions required to execute the image processing algorithm.

16. The system of claim 9 , wherein the first instructions are executable by a virtual processor that is part of a simulation environment for simulating performing the image processing algorithm by the image processor on the data specified by the two-dimensional address.

17. One or more non-transitory computer-readable storage media encoded with instructions that, when executed by one or more computers, cause the one or more computers to perform operations comprising:
receiving, by a compiler, first instructions of a first instruction set, wherein the first instructions define an image processing algorithm and comprise an instruction specifying, using a two-dimensional address comprising an x-coordinate and a y-coordinate, a position of data within a two-dimensional region of image data; and
translating, by the compiler, the first instructions into one or more second instructions of a second instruction set, wherein the second instruction set includes one or more shift instructions that are executable by an image processor comprising an array of execution lanes, wherein the second instructions are operable to cause the image processor to load, into a respective execution lane, the data within the two-dimensional region of image data at the position specified by the two-dimensional address using the one or more shift instructions,
wherein the one or more shift instructions when executed cause the two-dimensional region of image data to be shifted within a two-dimensional shift-register array of the image processor relative to the array of execution lanes.

18. The computer-readable storage media of claim 17 , wherein the operations further comprise:
causing the image processor to load the data specified by the two-dimensiona

Assignees

• Google Llc

Inventors

• Meixner Albert

Classifications

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F8/441 Primary

  Register allocation; Assignment of physical memory space to logical memory space · CPC title

• G06F9/345

  of multiple operands or results {(addressing multiple banks G06F12/06)} · CPC title

• G06F8/4441

  Reducing the execution time required by the program code · CPC title