Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure

Patent metadata

Field	Value
Publication number	US-10599407-B2
Application number	US-201816122801-A
Country	US
Kind code	B2
Filing date	Sep 5, 2018
Priority date	Apr 23, 2015
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.

First claim

What is claimed is:

1. A computer-implemented method comprising:
receiving a first sequence of instructions of a first instruction set architecture, wherein the first sequence of instructions (i) defines an image processing algorithm and (ii) includes one or more load instructions and one or more arithmetic instructions, wherein each load instruction specifies, using a two-dimensional address, a position of data within a region of image data;
receiving, by a compiler, a request to translate the first sequence of instructions into instructions of a second instruction set architecture, wherein instructions in the second instruction set architecture are executable by an image processor comprising a two-dimensional array of processing elements and a two-dimensional shift-register array, wherein each shift-register in the two-dimensional shift-register array is dedicated to a respective processing element in the two-dimensional array of processing elements; and
in response, translating the one or more load instructions in the first instruction set architecture into one or more shift instructions of the second instruction set architecture, wherein each shift instruction is operable to cause the image processor to shift data at the position within the region of image data specified by the two-dimensional address of a corresponding load instruction from a source register in the two-dimensional shift-register array to a destination register.

2. The computer-implemented method of claim 1 , wherein the translating comprises arranging the one or more shift instructions in an order that minimizes the total number of shift instructions required to execute the image processing algorithm.

3. The computer-implemented method of claim 1 , further comprising:
translating the one or more arithmetic instructions in the first instruction set architecture into corresponding arithmetic instructions in the second instruction set architecture, wherein each corresponding arithmetic instruction in the second instruction set architecture is operable to cause a processing element to which a respective destination register is dedicated to execute, on data shifted to the respective destination register, an arithmetic operation defined by the arithmetic instruction.

4. The computer-implemented method of claim 3 , wherein the processing element to which the destination register is dedicated executes the arithmetic operation between shift instructions.

5. The computer-implemented method of claim 1 , further comprising:
broadcasting the one or more shift instructions to the two-dimensional shift-register array.

6. The computer-implemented method of claim 1 , wherein the first sequence of instructions further includes a store instruction that specifies, using a two-dimensional address, a position of resultant data in a region of image data, and wherein the method further comprises:
translating the store instruction in the first instruction set architecture into a store instruction in the second instruction set architecture, wherein the store instruction in the second instruction set architecture is operable to cause the image processor to store the resultant data in an output line buffer.

7. The computer implemented method of claim 6 , wherein the resultant data is an output of the image processing algorithm, the output of the image processing algorithm having been generated as a result of executing the instructions of the second instruction set architecture.

8. A computer-implemented method comprising:
receiving a first sequence of instructions of a first instruction set architecture, wherein the first sequence of instructions (i) defines an image processing algorithm and (ii) includes a store instruction that specifies, using a two-dimensional address, a position of resultant data within a region of image data;
receiving, by a compiler, a request to translate the first sequence of instructions into instructions of a second instruction set architecture, wherein instructions in the second instruction set architecture are executable by an image processor comprising a two-dimensional array of processing elements and a two-dimensional shift-register array, wherein each shift-register in the two-dimensional shift-register array is dedicated to a respective processing element in the two-dimensional array of processing elements; and
in response, translating the store instruction in the first instruction set architecture into a store instruction in the second instruction set architecture, wherein the store instruction causes the image processor to store the resultant data in a line buffer.

9. A system comprising one or more computers and one or more storage devices storing instructions that operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
receiving a first sequence of instructions of a first instruction set architecture, wherein the first sequence of instructions (i) defines an image processing algorithm and (ii) includes one or more load instructions and one or more arithmetic instructions, wherein each load instruction specifies, using a two-dimensional address, a position of data within a region of image data;
receiving a request to translate the first sequence of instructions into instructions of a second instruction set architecture, wherein instructions in the second instruction set architecture are executable by an image processor comprising a two-dimensional array of processing elements and a two-dimensional shift-register array, wherein each shift-register in the two-dimensional shift-register array is dedicated to a respective processing element in the two-dimensional array of processing elements; and
in response, translating the one or more load instructions in the first instruction set architecture into one or more shift instructions of the second instruction set architecture, wherein each shift instruction is operable to cause the image processor to shift data at the position within the region of image data specified by the two-dimensional address of a corresponding load instruction from a source register in the two-dimensional shift-register array to a destination register.

10. The system of claim 9 , wherein the translating comprises arranging the one or more shift instructions in an order that minimizes the total number of shift instructions required to execute the image processing algorithm.

11. The system of claim 9 , wherein the operations further comprise:
translating the one or more arithmetic instructions in the first instruction set architecture into corresponding arithmetic instructions in the second instruction set architecture, wherein each corresponding arithmetic instruction in the second instruction set architecture is operable to cause a processing element to which a respective destination register is dedicated to execute, on data shifted to the respective destination register, an arithmetic operation defined by the arithmetic instruction.

12. The system of claim 11 , wherein the processing element to which the destination register is dedicated executes the arithmetic operation between shift instructions.

13. The system of claim 9 , wherein the operations further comprise:
broadcasting the one or more shift instructions to the two-dimensional shift-register array.

14. The system of claim 9 , wherein the first sequence of instructions further includes a store instruction that specifies, using a two-dimensional address, a position of resultant data in a region of image data, and wherein the operations further comprises:
translating the store instruction in the first instructio

Assignees

• Google Llc

Inventors

• Meixner Albert

Classifications

• G06F8/451 Primary

  Code distribution (considering CPU load at run-time G06F9/505; load rebalancing G06F9/5083) · CPC title

• G06F9/30003

  Arrangements for executing specific machine instructions · CPC title

• G06F9/345

  of multiple operands or results {(addressing multiple banks G06F12/06)} · CPC title

• G06F9/30134

  Register stacks; shift registers · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title