Device, a method used in forming a circuit structure, a method used in forming an array of elevationally-extending transistors and a circuit structure adjacent thereto

Patent metadata

Field	Value
Publication number	US-11177271-B2
Application number	US-201715705179-A
Country	US
Kind code	B2
Filing date	Sep 14, 2017
Priority date	Sep 14, 2017
Publication date	Nov 16, 2021
Grant date	Nov 16, 2021

Abstract

A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.

First claim

The invention claimed is:

1. A method used in forming a memory array comprising elevationally-extending strings of memory cells, comprising:
forming vertically-alternating tiers of different composition first and second materials in a memory array region and in a stair step region that is laterally adjacent the memory array region;
the vertically-alternating tiers being formed directly above a conductive-material tier that is in the memory-array region and in the stair step region, conductive lines in the stair step region that are directly below and vertically spaced from all of the conductive material of the conductive-material tier;
forming strings of transistor material comprising channel material through the vertically-alternating tiers in the memory array region directly against the conductive material of the conductive-material tier;
forming a stair step structure in the stair step region, the stair step structure comprising steps individually comprising the second material above the first material, the stair step structure comprising insulating material above the steps;
forming dummy structures and operative conductive vias in the stair step region that individually extend through the insulating material, through one of the steps, and through the vertically-alternating tiers at least some of the operative conductive vias individually comprising an upper conductive via that is directly electrically coupled to a lower conductive via, the lower conductive via being directly electrically coupled to one of the conductive lines and being directly against a bottom-most surface of and thereby directly electrically coupled to the conductive material of the conductive material tier, the dummy structures and the upper conductive vias individually comprising conducting material that is completely horizontally circumferentially surrounded by an insulator lining that is directly against sidewalls of the conducting material;
the conducting material of the upper conductive vias being directly against a top-most surface of and thereby directly electrically coupled to the conductive material of the conductive-material tier, the insulator lining that is completely horizontally circumferentially surrounding the conducting material of the upper conductive vias not extending through the conductive material of the conductive-material tier and having a bottom-most surface that is directly against the top-most surface of the conductive material of the conductive-material tier; and
after forming the dummy structures and the operative conductive vias, etching away at least a majority of the second material from the stair step structure.

2. The method of claim 1 wherein the etching etches away all of the second material from the stair step structure.

3. The method of claim 1 comprising forming horizontally-elongated trenches extending elevationally into the vertically-alternating tiers before the etching, the etching comprising flowing an etchant through the trenches to the second material.

4. The method of claim 1 comprising forming the stair step structure to comprise opposing first and second sets of the steps.

5. The method of claim 1 comprising forming multiple of the stair step structures with immediately adjacent of the stair step structures being separated from one another by an elevationally-outer landing.

6. The method of claim 5 comprising forming the stair step structure to comprise opposing first and second sets of the steps.

7. The method of claim 1 wherein the conducive material of the conductive-material tier comprises conductively-doped semiconductive material atop metal material.

8. The method of claim 1 wherein the conductive material of the conductive-material tier to which the conducting material of the at least some of the operative conductive vias is directly against being laterally spaced from all other of the conductive material of the conductive-material tier on both sides of individual of the at least some of the operative conductive vias in a vertical cross-section.

Assignees

• Micron Technology Inc

Inventors

• Tessariol Paolo
• Dorhout Justin B
• Chary Indra V
• Fang Jun
• Park Matthew
• Xie Zhiqiang
• Stull Scott D
• Osterberg Daniel
• Reece Jason
• Li Jian

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title