Atomic layer deposition and etch for reducing roughness

US11170997B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11170997-B2
Application numberUS-202016845746-A
CountryUS
Kind codeB2
Filing dateApr 10, 2020
Priority dateNov 21, 2017
Publication dateNov 9, 2021
Grant dateNov 9, 2021

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: depositing, in a plasma chamber, a first conformal layer on a patterned mask layer of a substrate by atomic layer deposition (ALD), wherein the substrate includes a first material layer and the patterned mask layer overlying the first material layer, the patterned mask layer having a first roughness prior to depositing the first conformal layer; and etching, in the plasma chamber, the first material layer to form a plurality of first patterned features of the first material layer defined by the patterned mask layer, wherein the plurality of first patterned features has a second roughness less than the first roughness of the patterned mask layer after etching the first material layer. 2. The method of claim 1 , wherein the first roughness corresponds to a first line edge roughness (LER) and a first line width roughness (LWR) and the second roughness corresponds to a second LER and a second LWR, wherein the second LER is equal to or less than about 2.0 nm and wherein the second LWR is equal to or less than about 2.0 nm. 3. The method of claim 1 , wherein a thickness of the first conformal layer is between about 0.5 nm and about 5 nm. 4. The method of claim 1 , further comprising: performing lithography and etching operations on a mask layer to form the patterned mask layer. 5. The method of claim 1 , wherein the patterned mask layer includes a photoresist material. 6. The method of claim 1 , wherein the patterned mask layer includes a hard mask material. 7. The method of claim 1 , wherein the patterned mask layer is configured to define one or more one-dimensional (1-D) features from the first material layer and one or more two-dimensional (2-D) features from the first material layer, wherein a critical dimension (CD) bias between the one or more 1-D features and the one or more 2-D features is substantially similar after etching the first material layer. 8. The method of claim 1 , wherein the patterned mask layer includes one or more isolated features in an isolated feature region and one or more dense features in a dense feature region having a greater feature density than the isolated feature region, wherein a CD bias between the one or more isolated features and the one or more dense features is substantially similar after etching the first material layer. 9. The method of claim 1 , wherein the substrate further includes a second material layer underlying the first material layer, the method further comprising: depositing, in the plasma chamber, a second conformal layer by ALD on exposed surfaces of the plurality of first patterned features, the patterned mask layer, and the second material layer; and etching, in the plasma chamber, the second material layer of the substrate to form a plurality of second patterned features defined by the plurality of first patterned features. 10. The method of claim 9 , wherein the plurality of second patterned features has a third roughness less than each of the first roughness and the second roughness. 11. The method of claim 10 , wherein the third roughness corresponds to a third LER and a third LWR, wherein the third LER is equal to or less than about 1.5 nm and wherein the third LWR is equal to or less than about 1.5 nm. 12. The method of claim 1 , wherein a critical dimension of the plurality of first patterned features is equal to or less than about 20 nm. 13. The method of claim 1 , wherein the first conformal layer includes silicon oxide (SiO x ). 14. The method of claim 1 , wherein depositing the first conformal layer by ALD includes: (a) introducing a precursor into the plasma chamber to adsorb on the patterned mask layer, (b) converting the precursor with plasma to form an adsorption-limited amount of the first conformal layer, and (c) repeating operations of introducing the precursor and converting the precursor until a desired thickness of the first conformal layer is deposited on the patterned mask layer.

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Inventors

Classifications

  • using subtractive patterning of the conductive members · CPC title

  • characterised by the processes involved to create the masks · CPC title

  • of masks comprising inorganic materials · CPC title

  • characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

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What does patent US11170997B2 cover?
Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implement…
Who is the assignee on this patent?
Lam Res Corp
What technology area does this patent fall under?
Primary CPC classification H10P14/6339. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 09 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).