Semiconductor device and manufacturing method of the same
US-2018090451-A1 · Mar 29, 2018 · US
US11166365B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11166365-B2 |
| Application number | US-201916663397-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 25, 2019 |
| Priority date | Nov 26, 2018 |
| Publication date | Nov 2, 2021 |
| Grant date | Nov 2, 2021 |
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A printed circuit board includes: a first insulating layer; and a heat radiating circuit pattern disposed on a first surface of the first insulating layer and having a pad and a via. The heat radiating circuit pattern includes: a first metal layer disposed on the first insulating layer; a graphite layer disposed on the first metal layer; and a second metal layer disposed on the graphite layer.
Opening claim text (preview).
What is claimed is: 1. A printed circuit board comprising: a first insulating layer; and a heat radiating circuit pattern disposed on a first surface of the first insulating layer and comprising a pad and a via, wherein the heat radiating circuit pattern comprises: a first metal layer disposed on the first insulating layer; a heat dispersing layer consisting of graphite disposed on the first metal layer; and a second metal layer disposed directly on the heat dispersing layer, and wherein the second metal layer is exposed onto the first surface of the first insulating layer, and wherein the second metal layer is in direct contact with at least one solder ball which is disposed above the via. 2. The printed circuit board of claim 1 , further comprising a first circuit pattern formed on a second surface of the first insulating layer opposite the first surface, wherein the heat dispersing layer forms a heat transfer path along a via land, a via hole and the first circuit pattern in the via. 3. The printed circuit board of claim 2 , wherein the first metal layer connects the via land, the via hole and the first circuit pattern together in the via; and the first metal layer, the heat dispersing layer, and the second metal layer fill the via hole. 4. The printed circuit board of claim 1 , further comprising an electronic element mounted on the first insulating layer and connected to the pad. 5. The printed circuit board of claim 1 , further comprising: a solder resist layer disposed on the first surface of the first insulating layer and exposing the pad; a second insulating layer disposed on a second surface of the first insulating layer opposite the first surface; and a second circuit pattern disposed on the second insulating layer. 6. A printed circuit board comprising: a first insulating layer; and a heat radiating circuit pattern comprising a via, and disposed on a first surface of the first insulating layer, wherein the heat radiating circuit pattern comprises: a first metal layer disposed on the first insulating layer; a heat dispersing layer consisting of graphite disposed on the first metal layer; and a second metal layer disposed directly on the heat dispersing layer, wherein the second metal layer is exposed onto the first surface of the first insulating layer, and wherein the second metal layer is in direct contact with at least one solder ball which is disposed above the via.
Use of materials for the {conductive, e.g. } metallic pattern · CPC title
by printed thermal vias · CPC title
Electroplating, e.g. finish plating · CPC title
Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer · CPC title
using internal conductor planes parallel to the surface for thermal conduction, e.g. power planes · CPC title
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