Shift register unit and driving method, gate driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-11151946-B2
Application number	US-201916641970-A
Country	US
Kind code	B2
Filing date	Jan 4, 2019
Priority date	Jan 4, 2019
Publication date	Oct 19, 2021
Grant date	Oct 19, 2021

Abstract

A shift register unit and a driving method, a gate driving circuit, and a display device are provided. The shift register unit includes an input terminal, a first shift register sub-unit, and a second shift register sub-unit. The first shift register sub-unit includes a first output terminal, is connected to the input terminal to receive an input signal, and is configured to output a first output signal at the first output terminal according to the input signal; the second shift register sub-unit includes a second output terminal, is connected to the input terminal to receive the input signal, and is configured to output a second output signal at the second output terminal according to the input signal; and a pulse portion of the first output signal at least partially overlaps with a pulse portion of the second output signal in time.

First claim

What is claimed is:

1. A shift register unit, comprising an input terminal, a first shift register sub-unit, and a second shift register sub-unit;
wherein the first shift register sub-unit comprises a first output terminal and is connected to the input terminal to receive an input signal, and the first shift register sub-unit is configured to output a first output signal at the first output terminal according to the input signal;
the second shift register sub-unit comprises a second output terminal and is connected to the input terminal to receive the input signal, and the second shift register sub-unit is configured to output a second output signal at the second output terminal according to the input signal; and
a pulse portion of the first output signal at least partially overlaps with a pulse portion of the second output signal in time;
wherein the first shift register sub-unit comprises a first input circuit and a first output circuit,
the first input circuit is connected to the input terminal and a first node, and is configured to input the input signal to the first node in response to a first clock signal; and
the first output circuit is connected to the first node and the first output terminal, and is configured to output the first output signal to the first output terminal under control of a level of the first node.

2. The shift register unit according to claim 1 , wherein the first input circuit comprises a first input transistor, a gate electrode of the first input transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the first input transistor is connected to the input terminal to receive the input signal, and a second electrode of the first input transistor is connected to the first node;
the first output circuit comprises a first output transistor and a first storage capacitor, a gate electrode of the first output transistor is connected to a third node, a first electrode of the first output transistor is connected to the first output terminal, and a second electrode of the first output transistor is connected to a second clock signal terminal to receive a second clock signal; and a first terminal of the first storage capacitor is connected to the gate electrode of the first output transistor, and a second terminal of the first storage capacitor is connected to the first electrode of the first output transistor.

3. The shift register unit according to claim 1 , wherein the first shift register sub-unit further comprises a first control circuit and an output noise reduction circuit;
the first control circuit is connected to a second node, and is configured to control a level of the second node in response to the level of the first node and the first clock signal; and
the output noise reduction circuit is connected to the first output terminal, and is configured to perform noise reduction on the first output terminal under control of the level of the second node.

4. The shift register unit according to claim 3 , wherein the first control circuit comprises a first transistor and a second transistor;
a gate electrode of the first transistor is connected to the first node, a first electrode of the first transistor is connected to a first clock signal terminal to receive the first clock signal, and a second electrode of the first transistor is connected to the second node; and
a gate electrode of the second transistor is connected to the first clock signal terminal to receive the first clock signal, a first electrode of the second transistor is connected to a first voltage terminal to receive a first voltage, and a second electrode of the second transistors is connected to the second node.

5. The shift register unit according to claim 3 , wherein the output noise reduction circuit comprises a third transistor and a first capacitor;
a gate electrode of the third transistor is connected to the second node, a first electrode of the third transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the third transistor is connected to the first output terminal; and
a first terminal of the first capacitor is connected to the second node, and a second terminal of the first capacitor is connected to the first electrode of the third transistor.

6. The shift register unit according to claim 3 , wherein the first shift register sub-unit further comprises a first node noise reduction circuit; and
the first node noise reduction circuit is connected to the first node and the second node, and is configured to perform noise reduction on the first node under control of the level of the second node and a second clock signal.

7. The shift register unit according to claim 6 , wherein the first node noise reduction circuit comprises a fourth transistor and a fifth transistor;
a gate electrode of the fourth transistor is connected to the second node, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to a first electrode of the fifth transistor; and
a gate electrode of the fifth transistor is connected to a second clock signal terminal to receive the second clock signal, and a second electrode of the fifth transistor is connected to the first node.

8. The shift register unit according to claim 1 , wherein the first shift register sub-unit further comprises a voltage stabilization circuit;
the voltage stabilization circuit is connected to the first node and a third node, and is configured to stabilize a level of the third node; and
the first output circuit is connected to the third node, and is configured to output the first output signal to the first output terminal under control of the level of the third node.

9. The shift register unit according to claim 8 , wherein the voltage stabilization circuit comprises a sixth transistor,
a gate electrode of the sixth transistor is connected to a first voltage terminal to receive a first voltage, a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected to the third node.

10. The shift register unit according to claim 1 , wherein the second shift register sub-unit comprises a second input circuit, a second output circuit, a second control circuit, and an output reset circuit;
the second input circuit is connected to the input terminal and a fourth node, and is configured to input the input signal to the fourth node in response to a first clock signal;
the second output circuit is connected to the fourth node and the second output terminal, and is configured to output the second output signal to the second output terminal under control of a level of the fourth node;
the second control circuit is connected to the fourth node and a fifth node, and is configured to control a level of the fifth node in response to the level of the fourth node and a third clock signal; and
the output reset circuit is connected to the fifth node, and is configured to reset the second output terminal under control of the level of the fifth node.

11. The shift register unit according to claim 10 , wherein the second input circuit comprises a second input transistor, a gate electrode of the second input transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the second input transistor is connected to the input terminal to receive the input signal, and a second electrode of the second input transistor is connected to the fourth node;
the second output circuit comprises a second output transistor and a second storag

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shi Lubin
• Chen Xiaohai
• Zhou Tingting

Classifications

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title