Shift register and a method for driving the same, a gate driving circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-10467966-B2
Application number	US-201615214401-A
Country	US
Kind code	B2
Filing date	Jul 19, 2016
Priority date	Jan 5, 2016
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

According to the embodiments of the disclosure, a shift register and a method for driving the same, a gate driving circuit and a display apparatus may be provided. The shift register includes an input module, a node control module, a first output module and a second output module. The input module may control a potential at a first node via an input signal end and a first clock signal end, the node control module may configured to control the potential at a first node via a first control signal end and a DC signal end, the first output module may control the potential at a driving signal output end via a second control signal end and the DC signal end, and the second output module may maintain a voltage difference between the first node and the driving signal output end in a stable state when the first node is in a floating state and control the potential at the driving signal output end via the first node and the second clock signal end. By cooperating with each other, these four modules may achieve the outputs of scanning signals with a simpler structure and a fewer signal lines, so as to simplify the manufacturing process and reduce the production cost.

First claim

I claim:

1. A shift register, comprising:
an input module having a first end connected to an input signal end, a second end connected to a first clock signal end, and a third end connected to a first node, the input module being configured to provide a signal from the input signal end to the first node under the control of the first clock signal end;
a node control module having a first end connected to a DC signal end, a second end connected to a first control signal end and a third end connected to the first node, the node control module being configured to provide a signal from the DC signal end to the first node under the control of the first control signal end;
a first output module having a first end connected to the DC signal end, a second end connected to a second control signal end, and a third end connected to a driving signal output end of the shift register, the first output module being configured to provide the signal from the DC signal end to the driving signal output end under the control of the second control signal end; and
a second output module having a first end connected to a second clock signal end, a second end connected to the first node, and a third end connected to the driving signal output end, the second output module being configured to provide a signal from the second clock signal end to the driving signal output end under the control of the first node and to maintain a voltage difference between the first node and the driving signal output end in a stable state when the first node is in a floating state,
wherein the input module and the node control module are configured such that the first node is in the floating state under the control of the first clock signal end and the first control signal end, and
when a signal from the first clock signal end is at an active level, a signal from the first control signal end comprises an inactive period and an active period, such that the voltage difference between the first node and the driving signal output end is maintained to be in the stable state.

2. The shift register of claim 1 , wherein the input module further comprises a first switch transistor having a source connected to the input signal end, a gate connected to the first clock signal end, and a drain connected to the first node.

3. The shift register of claim 1 , wherein the node control module further comprises a second switch transistor having a source connected to the DC signal end, a gate connected to the first control signal end, and a drain connected to the first node.

4. The shift register of claim 1 , wherein the first output module further comprises a third switch transistor having a source connected to the DC signal end, a gate connected to the second control signal end, and a drain connected to the driving signal output end.

5. The shift register of claim 1 , wherein the second output module further comprises a fourth switch transistor and a capacitor,
wherein the fourth switch transistor has a source connected to the second clock signal end, a gate connected to the first node, and a drain connected to the driving signal output end, and
the capacitor has a first end connected to the first node and a second end connected to the driving signal output end.

6. The shift register of claim 1 , wherein the first control signal end and the second control signal end are the same control signal end.

7. A method for driving the shift register of claim 1 , comprising:
in a first phase, providing, by the node control module, the signal from the DC signal end to the first node under the control of the first control signal end, and providing, by the first output module, the signal from the DC signal end to the driving signal output end under the control of the second control signal end;
in a second phase, providing, by the input module, the signal from the input signal end to the first node under the control of the first clock signal end, and providing, by the second output module, the signal from the second clock signal end to the driving signal output end under the control of the first node;
in a third phase, the first node being in a floating state, and maintaining a voltage difference between the first node and the driving signal output end in a stable state, and providing, by the second output module, the signal from the second clock signal end to the driving signal output end under the control of the first node; and
in a fourth phase, providing, by the input module, the signal from the input signal end to the first node under the control of the first clock signal end, providing, by the node control module, the signal from the DC signal end to the first node under the control of the first control signal end; and providing, by the first output module, the signal from the DC signal end to the driving signal output end under the control of the second control signal end,
wherein the first node is in the floating state under the control of the first clock signal end and the first control signal end, and
when a signal from the first clock signal end is at an active level, a signal from the first control signal end comprises an inactive period and an active period, such that the voltage difference between the first node and the driving signal output end is maintained to be in the stable state.

8. A gate driving circuit comprising a plurality of cascaded shift registers of claim 1 , wherein:
an input signal end of a first stage of shift register is connected to a frame trigger signal end; and
each of input signal ends of remaining various stages of shift registers except for the first stage of shift register is connected to a driving signal output end of a previous stage of shift register.

9. A display apparatus comprising the gate driving circuit of claim 8 .

10. The display apparatus of claim 9 , wherein the display apparatus is an organic light emitting display (OLED) apparatus.

11. The display apparatus of claim 10 , wherein the OLED apparatus comprise a plurality of pixel circuits which are arranged in an array and configured to at least have light emitting control signal ends and scanning signal ends, and
wherein each row of the pixel circuits corresponds to a shift register in the gate driving circuit, the light emitting control signal end of each row of the pixel circuits being connected to the first control signal end and the second control signal end of the corresponding shift register, and the scanning signal end of each row of the pixel circuits being connected to the driving signal output end of the corresponding shift register.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Ma Zhanjie

Classifications

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title