Efficiency for coordinated start interpretive execution exit for a multithreaded processor

Patent metadata

Field	Value
Publication number	US-11150905-B2
Application number	US-201715717487-A
Country	US
Kind code	B2
Filing date	Sep 27, 2017
Priority date	Oct 20, 2014
Publication date	Oct 19, 2021
Grant date	Oct 19, 2021

Abstract

A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

First claim

What is claimed is:

1. A processor-implemented method of executing a plurality of threads including a first thread and a set of remaining threads, the method executed on a computer processor core, the processor-implemented method comprising:
determining that a warning track interruption pending condition exists for the first thread;
entering a start interpretive execution exit sync loop based on the determining that the warning track interruption pending condition exists, wherein the start interpretive execution exit sync loop is entered based on the determining that the warning track interruption pending condition exists without presenting warning track interruption and without signaling each of the set of remaining threads;
determining a grace period has expired for the computer processor core; and
signaling, by the first thread, each of the set of remaining threads to proceed to a corresponding start interpretive execution exit sync loop based on expiration of the grace period.

2. The processor-implemented method of claim 1 , the processor-implemented method comprising:
determining that a start interpretive execution exit condition exists;
entering by the first thread the start interpretive execution exit sync loop without signaling to any of the set of remaining threads; and
remaining by the first thread in the start interpretive execution exit sync loop until the grace period expires or each of the set of remaining threads enters the corresponding start interpretive execution exit sync loop.

3. The processor-implemented method of claim 1 , wherein the first thread is a primary thread of the plurality of threads.

4. A system comprising a processor and a memory, the system executing a plurality of threads on a computer processor core of the processor, the plurality of threads including a first thread and a set of remaining threads, the processor being configured to:
determine that a warning track interruption pending condition exists for the first thread;
enter a start interpretive execution exit sync loop based on the determining that the warning track interruption pending condition exists, wherein the start interpretive execution exit sync loop is entered based on the determining that the warning track interruption pending condition exists without presenting warning track interruption and without signaling each of the set of remaining threads;
determine a grace period has expired for the computer processor core; and
signal, by the first thread, each of the set of remaining threads to proceed to a corresponding start interpretive execution exit sync loop based on expiration of the grace period.

5. The system of claim 4 , the processor being configured to:
determine that a start interpretive execution exit condition exists;
enter by the first thread the start interpretive execution exit sync loop without signaling to any of the set of remaining threads; and
remain by the first thread in the start interpretive execution exit sync loop until the grace period expires or each of the set of remaining threads enters the corresponding start interpretive execution exit sync loop.

6. The system of claim 4 , wherein the first thread is a primary thread of the plurality of threads.

7. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions for executing a plurality of threads on a computer processor core of a processor, the plurality of threads including a first thread and a set of remaining threads, the program instructions executable by the processor to cause the processor to:
determine that a warning track interruption pending condition exists for the first thread;
enter a start interpretive execution exit sync loop based on the determining that the warning track interruption pending condition exists, wherein the start interpretive execution exit sync loop is entered based on the determining that the warning track interruption pending condition exists without presenting warning track interruption and without signaling each of the set of remaining threads;
determine a grace period has expired for the computer processor core; and
signal, by the first thread, each of the set of remaining threads to proceed to a corresponding start interpretive execution exit sync loop based on expiration of the grace period.

8. The computer program product of claim 7 , the program instructions executable by the processor to cause the processor to:
determine that a start interpretive execution exit condition exists;
enter by the first thread the start interpretive execution exit sync loop without signaling to any of the set of remaining threads; and
remain by the first thread in the start interpretive execution exit sync loop until the grace period expires or each of the set of remaining threads enters the corresponding start interpretive execution exit sync loop.

9. The computer program product of claim 7 , wherein the first thread is a primary thread of the plurality of threads.

Assignees

• IBM

Inventors

• Bradbury Jonathan D
• Busaba Fadi Y
• Farrell Mark S
• Gainey Jr Charles W
• Greiner Dan F
• Heller Lisa C
• Kubala Jeffrey P
• Osisek Damian L
• Schmidt Donald W
• Siegel Timothy J

Classifications

• G06F9/45533 Primary

  Hypervisors; Virtual machine monitors · CPC title

• G06F9/522

  Barrier synchronisation · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30065 Primary

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title