Efficiency for coordinated start interpretive execution exit for a multithreaded processor

Patent metadata

Field	Value
Publication number	US-2016110218-A1
Application number	US-201514844223-A
Country	US
Kind code	A1
Filing date	Sep 3, 2015
Priority date	Oct 20, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop

First claim

What is claimed is:

1 . A method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core, the method comprising:
determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads; and remaining by the first thread in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

2 . The method of claim 1 , further comprising:
determining that the first thread is pending for a warning track interruption; propagating warning track interruption pending condition by the first thread to each of remaining threads; and causing, by the first thread, the computer processor core to enter the grace period.

3 . The method of claim 1 , further comprising:
determining the grace period has expired for the computer processor core; signaling, by the first thread, each of the remaining threads to proceed to the corresponding start interpretive execution exit sync loop based on expiration of the grace period.

4 . The method of claim 1 , further comprising:
determining that a wait state is pending for the first thread; determining that a warning track interruption pending condition exists for the first thread; and entering the start interpretive execution exit sync loop based on the determining that the warning track interruption pending condition exists.

5 . The method of claim 4 , wherein the start interpretive execution exit sync loop is entered based on the determining that the warning track interruption pending condition exists without presenting warning track interruption and without signaling each of the remaining threads.

6 . The method of claim 1 , wherein the first thread is a primary thread of the plurality of threads.

7 . A method of implementing a wait state for a plurality of threads executing on a computer processor core, the method comprising:
executing instruction streams by the plurality of threads, the plurality of threads including a first thread and a set of remaining threads; determining that the first thread has entered a first wait state loop; determining that any of the remaining threads has not entered a corresponding wait state loop; and remaining by the first thread in the first wait state loop until each of the remaining threads has entered the corresponding wait state loop.

8 . The method of claim 7 , further comprising:
exiting the first wait state loop in response to an asynchronous interrupting pending on the first thread.

9 . The method of claim 7 , further comprising:
exiting the first wait state loop in response to receiving a start interpretive execution exit request signal from one of the remaining threads.

Assignees

• IBM

Inventors

• Bradbury Jonathan D
• Busaba Fadi Y
• Farrell Mark S
• Gainey Charles W
• Greiner Dan F
• Heller Lisa C
• Kubala Jeffrey P
• Osisek Damian L
• Schmidt Donald W
• Slegel Timothy J

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/45533 Primary

  Hypervisors; Virtual machine monitors · CPC title

• G06F9/30065 Primary

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F9/522

  Barrier synchronisation · CPC title

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title