Efficiency for coordinated start interpretive execution exit for a multithreaded processor

Patent metadata

Field	Value
Publication number	US-2018018174-A1
Application number	US-201715717279-A
Country	US
Kind code	A1
Filing date	Sep 27, 2017
Priority date	Oct 20, 2014
Publication date	Jan 18, 2018
Grant date	—

Abstract

A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

First claim

What is claimed is:

1 . A system comprising a processor and a memory, the system implementing a wait state for a plurality of threads executing on a computer processor core of the processor, the processor being configured to:
execute instruction streams by the plurality of threads, wherein the plurality of threads includes a first thread and a set of remaining threads; determine that the first thread has entered a first wait state loop; determine that any of the remaining threads has not entered a corresponding wait state loop; and remain by the first thread in the first wait state loop until each of the remaining threads has entered the corresponding wait state loop.

2 . The system of claim 1 , the processor being configured to:
exit the first wait state loop in response to an asynchronous interrupting pending on the first thread.

3 . The system of claim 2 , the processor being configured to:
enter a firmware asynchronous interruption handler by the first thread.

4 . The system of claim 3 , wherein the firmware asynchronous interruption handler saves interruption information into a fixed storage location in the memory.

5 . The system of claim 1 , the processor being configured to:
exit the first wait state loop in response to receiving a start interpretive execution exit request signal from one of the remaining threads.

6 . The system of claim 1 , wherein a second thread independently executes guest instructions, loads an enabled wait state, and enters a firmware wait state loop.

7 . The system of claim 6 , wherein a third thread independently executes guest instructions, loads an enabled wait state, and enters a firmware wait state loop.

8 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions implementing a wait state for a plurality of threads executing on a computer processor core of a processor, the program instructions executable by the processor to cause the processor to:
execute instruction streams by the plurality of threads, wherein the plurality of threads includes a first thread and a set of remaining threads; determine that the first thread has entered a first wait state loop; determine that any of the remaining threads has not entered a corresponding wait state loop; and remain by the first thread in the first wait state loop until each of the remaining threads has entered the corresponding wait state loop.

9 . The computer program product of claim 8 , the program instructions executable by the processor to cause the processor to:
exit the first wait state loop in response to an asynchronous interrupting pending on the first thread.

10 . The computer program product of claim 9 , the program instructions executable by the processor to cause the processor to:
enter a firmware asynchronous interruption handler by the first thread.

11 . The computer program product of claim 10 , wherein the firmware asynchronous interruption handler saves interruption information into a fixed storage location in the memory.

12 . The computer program product of claim 8 , the program instructions executable by the processor to cause the processor to:
exit the first wait state loop in response to receiving a start interpretive execution exit request signal from one of the remaining threads.

13 . The computer program product of claim 8 , wherein a second thread independently executes guest instructions, loads an enabled wait state, and enters a firmware wait state loop.

14 . The computer program product of claim 13 , wherein a third thread independently executes guest instructions, loads an enabled wait state, and enters a firmware wait state loop.

15 . A processor-implemented method implementing a wait state for a plurality of threads executing on a computer processor core of a processor, the processor-implemented method comprising:
executing instruction streams by the plurality of threads, wherein the plurality of threads includes a first thread and a set of remaining threads; determining that the first thread has entered a first wait state loop; determining that any of the remaining threads has not entered a corresponding wait state loop; and remaining by the first thread in the first wait state loop until each of the remaining threads has entered the corresponding wait state loop.

16 . The processor-implemented method of claim 15 , the processor-implemented method comprising:
exit the first wait state loop in response to an asynchronous interrupting pending on the first thread.

17 . The processor-implemented method of claim 16 , the processor-implemented method comprising:
enter a firmware asynchronous interruption handler by the first thread.

18 . The processor-implemented method of claim 17 , wherein the firmware asynchronous interruption handler saves interruption information into a fixed storage location in the memory.

19 . The processor-implemented method of claim 15 , the processor-implemented method comprising:
exit the first wait state loop in response to receiving a start interpretive execution exit request signal from one of the remaining threads.

20 . The processor-implemented method of claim 15 , wherein a second thread independently executes guest instructions, loads an enabled wait state, and enters a firmware wait state loop.

Assignees

• IBM

Inventors

• Bradbury Jonathan D
• Busaba Fadi Y
• Farrell Mark S
• Gainey Jr Charles W
• Greiner Dan F
• Heller Lisa C
• Kubala Jeffrey P
• Osisek Damian L
• Schmidt Donald W
• Slegel Timothy J

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/522

  Barrier synchronisation · CPC title

• G06F9/45533 Primary

  Hypervisors; Virtual machine monitors · CPC title

• G06F9/30065 Primary

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title