Method and apparatus for testing a semiconductor device

Patent metadata

Field	Value
Publication number	US-11150296-B2
Application number	US-201916726467-A
Country	US
Kind code	B2
Filing date	Dec 24, 2019
Priority date	Sep 6, 2011
Publication date	Oct 19, 2021
Grant date	Oct 19, 2021

Abstract

The present disclosure provides methods for testing and evaluating electrical parameters of electronic circuits. An exemplary method includes providing a device-under-test electrically coupled to a testing apparatus; and determining an optimum value of a first electrical parameter and an optimum value of a second parameter by testing the device-under-test according to a set of first electrical parameter values and a set of second electrical parameter values. The optimum value of the first electrical parameter and the optimum value of the second parameter are determined based on an electrical noise response of the device-under-test.

First claim

What is claimed is:

1. A method comprising:
providing a device under test electrically coupled to a testing apparatus;
applying a first voltage to the device under test and a second voltage to the testing apparatus;
detecting, in response to the applying, electrical noise generated by the testing apparatus;
repeating the applying and the detecting a plurality of times by changing values of the first voltage and the second voltage during each repetition;
identifying a first optimum value of the first voltage and a second optimum value of the second voltage that correspond to a minimum amount of electrical noise; and
testing the device under test using the first optimum value of the first voltage and the second optimum value of the second voltage.

2. The method of claim 1 , wherein:
the repeating includes executing a nested loop that includes an inner loop and an outer loop, the inner loop being situated within the outer loop;
the inner loop includes a first sweep of the first voltage; and
the outer loop includes a second sweep of the second voltage.

3. The method of claim 2 , wherein:
the executing the nested loop yields the second optimum value of the second voltage; and
the repeating further includes, after the nested loop is executed, performing a third sweep of the first voltage that yields the first optimum value of the first voltage, the third sweep being performed while the second voltage is maintained at the second optimum value.

4. The method of claim 1 , wherein:
the first voltage is a device terminal voltage; and
the second voltage is a power supply voltage.

5. The method of claim 1 , wherein:
the device under test includes at least one of: a resistor and a transistor;
the testing apparatus includes a plurality of electronic switches and a plurality of memory storage elements; and
the electrical noise includes leakage current of the testing apparatus.

6. The method of claim 1 , wherein the providing the device under test electrically coupled to the testing apparatus includes selectively activating a subset of electronic switches to establish electrical coupling between the device under test and a subset of testing pads of the testing apparatus.

7. The method of claim 1 , further including executing one or more of the applying, the detecting, the repeating, the identifying, and the testing for a plurality of additional device under tests as a part of parallel testing processes.

8. The method of claim 7 , wherein the testing apparatus includes at least a subset of testing pads that are shared between the device under test and the plurality of additional device under tests.

9. A method comprising:
electrically coupling a device-under-test to a testing apparatus;
applying device terminal voltages to the device-under-test;
applying power supply voltages to the testing apparatus;
measuring an electrical noise response of the testing apparatus during the applying the device terminal voltages and the power supply voltages to determine an optimum device terminal voltage and an optimum power supply voltage that minimize the electrical noise response of the testing apparatus; and
testing the device-under-test using the optimum device terminal voltage and the optimum power supply voltage.

10. The method of claim 9 , wherein the electrical noise response corresponds with leakage current of the testing apparatus.

11. The method of claim 9 , wherein:
the applying the device terminal voltages to the device-under-test includes sweeping across a desired range of the device terminal voltages while a fixed power supply voltage is applied to the testing apparatus; and
the applying the power supply voltages to the testing apparatus includes sweeping across a desired range of the power supply voltages while a fixed device terminal voltage is applied to the device-under-test.

12. The method of claim 11 , wherein the sweeping across the desired range of the device terminal voltages is an inner loop of a nested loop sweeping process and the sweeping across the desired range of the power supply voltages is an outer loop of the nested loop sweeping process.

13. The method of claim 11 , wherein the sweeping across the desired range of the device terminal voltages and the sweeping across the desired range of the power supply voltages use different step sizes.

14. The method of claim 11 , wherein the sweeping across the desired range of the device terminal voltages is performed before the sweeping across the desired range of the power supply voltages.

15. The method of claim 9 , wherein the device-under-test is one of a plurality of device-under-tests and electrically coupling the device-under-test to the testing apparatus includes selectively activating a subset of switching devices to electrically couple the one of the plurality of device-under-tests to a subset of testing pads of the testing apparatus.

16. The method of claim 15 , wherein selectively activating the subset of switching devices to electrically couple the one of the plurality of device-under-tests to the subset of testing pads of the testing apparatus includes receiving signals from at least one flip flop device.

17. An apparatus comprising a non-transitory, tangible computer readable storage medium storing a computer program, wherein the computer program contains instructions that when executed, perform:
performing a first sweeping process with respect to a first electrical parameter and a second electrical parameter, the first sweeping process being performed on a testing unit and an electronic circuit communicatively coupled to the testing unit;
determining a first optimum value of the first electrical parameter in response to the first sweeping process, the first optimum value being a value that yields a lower electrical noise than other values of the first electrical parameter;
thereafter, performing a second sweeping process with respect to the second electrical parameter, the second sweeping process being performed while the first electrical parameter is maintained at the first optimum value;
determining a second optimum value of the second electrical parameter in response to the second sweeping process, the second optimum value being a value that yields a lower electrical noise than other values of the second electrical parameter; and
testing the testing unit using the first optimum value and the second optimum value for the first electrical parameter and the second electrical parameter, respectively.

18. The apparatus of claim 17 , wherein:
the first electrical parameter includes a power supply voltage;
the second electrical parameter includes a device terminal voltage; and
the first sweeping process is executed using a nested loop, the device terminal voltage being a variable of an inner loop of the nested loop, and the power supply voltage being a variable of an outer loop of the nested loop.

19. The apparatus of claim 17 , wherein:
the electronic circuit contains a plurality of electronic switching devices that are operable to selectively establish communication between the testing unit and a plurality of testing pads;
the instructions for performing the first sweeping process and the instructions for performing the second sweeping process each contain instructions for deactivating at least a subset of the electronic switching devices; and
the instructions for testing the testing unit contain instructions for activating at least a subset of the electronic switching devices.

20. The apparatus of claim 17 , where

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Szu-Chia
• Shao Jhih Jie
• Chung Tang-Hsuan
• Tseng Huan Chi

Classifications

• G01R31/30 Primary

  Marginal testing, e.g. by varying supply voltage (testing computers during standby operation or idle time G06F11/22) · CPC title

• G01R31/3004

  Current or voltage test · CPC title