Residue removal in metal gate cutting process

Patent metadata

Field	Value
Publication number	US-11145752-B2
Application number	US-201916572831-A
Country	US
Kind code	B2
Filing date	Sep 17, 2019
Priority date	Sep 17, 2019
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

A method includes forming a gate dielectric layer, forming a metal gate strip over a bottom portion of the gate dielectric layer, and performing a first etching process on the metal gate strip to remove a portion of the metal gate strip. The first etching process is performed anisotropically. After the first etching process, a second etching process is performed on the metal gate strip to remove a residue portion of the metal gate strip. The second etching process includes an isotropic etching process. A dielectric material is filled into a recess left by the etched portion and the etched residue portion of the metal gate strip.

First claim

What is claimed is:

1. A method comprising:
forming a gate dielectric layer;
forming a metal gate strip over a bottom portion of the gate dielectric layer;
forming a hard mask over the metal gate strip;
patterning the hard mask;
performing a first etching process on the metal gate strip to remove a portion of the metal gate strip, wherein the first etching process is performed anisotropically;
oxidizing the hard mask to form a protection layer on a sidewall of the hard mask;
after the first etching process, performing a second etching process on the metal gate strip to remove a residue portion of the metal gate strip, wherein the second etching process comprises an isotropic etching process, and wherein the protection layer is exposed to the second etching process; and
filling a dielectric material into a recess left by the etched portion and the etched residue portion of the metal gate strip.

2. The method of claim 1 , wherein the first etching process is performed until a dielectric dummy fin underlying the metal gate strip is exposed.

3. The method of claim 2 , wherein the first etching process is performed until a corresponding recess generated by the etched portion of the metal gate strip has a bottom surface lower than a top surface of the dielectric dummy fin, and the residue portion comprises a lower portion lower than the top surface and an upper portion higher than the top surface.

4. The method of claim 1 , wherein the second etching process is performed using an etching gas comprising tungsten fluoride.

5. The method of claim 4 , wherein the etching gas further comprises tungsten chloride.

6. The method of claim 1 , wherein the first etching process is performed with plasma, and the second etching process comprises a thermal etching process without plasma.

7. The method of claim 1 , wherein in the second etching process, a tip portion of the gate dielectric layer at a same level as the residue portion of the metal gate strip is further etched.

8. The method of claim 1 , wherein the first etching process and the second etching process are performed using a same etching mask.

9. A method comprising:
forming a gate stack over and contacting a dielectric dummy fin, wherein the gate stack comprises:
a first portion on a first side of the dielectric dummy fin;
a second portion on a second side of the dielectric dummy fin;
a third portion overlapping the gate stack, wherein the third portion interconnects the first portion and the second portion;

etching the third portion, a first part of the first portion, and a second part of the second portion of the gate stack to reveal a top surface and sidewalls of the dielectric dummy fin, wherein after the etching, a residue portion of the third portion is left, and the residue portion interconnects the first portion and the second portion; and
etching the residue portion.

10. The method of claim 9 , wherein the first portion and the second portion form metal gates of a first Fin Field-Effect Transistor (FinFET) and a second FinFET, respectively.

11. The method of claim 9 , wherein the etching the third portion is performed using an etching gas comprising a metal fluoride.

12. The method of claim 11 , wherein the metal fluoride comprises tungsten fluoride.

13. The method of claim 9 further comprising:
forming a silicon-containing mask layer over the gate stack;
etching the silicon-containing mask layer to form an opening penetrating through the silicon-containing mask layer; and
performing an oxidation process to oxidize exposed portions of the silicon-containing mask layer to form a protection layer, wherein the protection layer is exposed when the residue portion is etched.

14. The method of claim 9 , wherein the residue portion comprises a portion of a gate dielectric of the gate stack, and a portion of a metal gate of the gate stack, and in the etching the residue portion, the portion of the gate dielectric and the portion of the metal gate are removed.

15. A method comprising:
forming a metal gate strip;
forming an amorphous layer over the metal gate strip;
forming a patterned hard mask over the amorphous layer;
etching the amorphous layer using the patterned hard mask as an etching mask, wherein the metal gate strip is revealed;
etching the metal gate strip to form a recess in the metal gate strip, wherein the recess has a bottom surface lower than a top surface of an underlying dielectric dummy fin, and the top surface and opposite sidewalls of the underlying dielectric dummy fin are exposed to the recess;
performing a thermal etching process to remove a residue portion of the metal gate strip; and
filling a dielectric material into the recess.

16. The method of claim 15 , wherein after the etching the metal gate strip, sidewalls of gate spacers are exposed to the recess, and the gate spacers are on opposite sides of the recess, and the gate spacers are not etched in the etching the metal gate strip.

17. The method of claim 15 further comprising, after the etching the amorphous layer and before the etching the metal gate strip, oxidizing a surface portion of the amorphous layer.

18. The method of claim 17 , wherein the oxidizing is performed using water steam and ammonia as process gases.

19. The method of claim 15 , wherein the etching the metal gate strip is performed using a process gas comprising a metal fluoride.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Feng Chieh-Ning
• Hung Chih-Chang
• Chen Bing-Hung
• Lin Yih-Ann

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D84/0158 Primary

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title