Fin Field-Effect Transistor Devices and Methods of Forming the Same

Patent metadata

Field	Value
Publication number	US-2020105613-A1
Application number	US-201916248242-A
Country	US
Kind code	A1
Filing date	Jan 15, 2019
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

First claim

1 . A method of forming a semiconductor device, the method comprising:
forming a first fin and a second fin that protrude above a substrate; forming isolation regions on opposing sides of the first fin and on opposing sides of the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, wherein the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, wherein the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, wherein the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

2 . The method of claim 1 , wherein forming the metal gate comprises:
forming a dummy gate over the first fin and over the second fin; forming the first dielectric layer around the dummy gate; and replacing the dummy gate with the metal gate.

3 . The method of claim 1 , further comprising filling the recess with a dielectric material, wherein after filling the recess with the dielectric material, the metal gate is separated into a first metal gate over the first fin and a second metal gate over the second fin.

4 . The method of claim 1 , wherein the recess extends from the upper surface of the metal gate to an opposing lower surface of the metal gate, wherein the recess exposes at least a portion of the isolation regions.

5 . The method of claim 1 , wherein the method further comprises forming a third fin between the first fin and the second fin, wherein the recess is formed over the third fin, and is formed to extend from the upper surface of the metal gate to the third fin.

6 . The method of claim 1 , wherein forming the recess comprises:
forming a patterned mask layer over the metal gate and over the first dielectric layer, the patterned mask layer having an opening over a portion of the metal gate between the first fin and the second fin; and performing an etching process using the patterned mask layer as an etching mask to form the recess.

7 . The method of claim 6 , wherein performing the etching process comprises performing a plurality of etching cycles, wherein each of the plurality of etching cycles comprises:
forming a protection layer along sidewalls of the metal gate exposed by the recess; and etching the metal gate using an etchant.

8 . The method of claim 7 , wherein forming the protection layer comprises depositing the protection layer over the sidewalls of the metal gate.

9 . The method of claim 8 , wherein depositing the protection layer comprises depositing the protection layer using a first precursor comprising silicon and a second precursor comprising oxygen, wherein etching the metal gate comprising etching the metal gate using an etching gas comprising boron trichloride.

10 . The method of claim 6 , further comprising, before forming the recess in the metal gate:
recessing the upper surface of the metal gate below an upper surface of the first dielectric layer; and forming a sacrificial layer over the recessed upper surface of the metal gate and over the upper surface of the first dielectric layer.

11 . The method of claim 10 , wherein performing the etching process comprises performing a plurality of etching cycles, wherein each of the plurality of etching cycles comprises:
converting portions of the sacrificial layer exposed by the recess into a protection layer; and etching the metal gate using an etchant.

12 . The method of claim 11 , wherein the sacrificial layer comprises amorphous silicon, and the protection layer comprises silicon oxide, wherein etching the metal gate comprising etching the metal gate using an etching gas comprising chlorine.

13 . A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer around a dummy gate structure, the dummy gate structure disposed over a first fin and a second fin; replacing the dummy gate structure with a metal gate structure; forming a patterned mask layer over the metal gate structure and the first dielectric layer, wherein the patterned mask layer has an opening over the metal gate structure; performing an etching process to form a recess aligned with the opening of the patterned mask layer, wherein the etching process comprises a plurality of etching cycles, wherein each of the plurality of etching cycles comprises:
forming a protection layer in the recess; and
removing portions of the metal gate structure using an etchant that is selective to materials of the metal gate structure; and
filling the recess with a second dielectric material.

14 . The method of claim 13 , wherein the recess extends through the metal gate structure and exposes a portion of an isolation region between the first fin and the second fin.

15 . The method of claim 13 , wherein the dummy gate structure is also disposed over a dummy fin between the first fin and the second fin, wherein the recess is formed over the dummy fin, and a lower portion of the recess exposes a top portion of the dummy fin.

16 . The method of claim 13 , wherein the recess extends from an upper surface of the metal gate structure into the metal gate structure, wherein along a longitudinal direction of the metal gate structure, an upper portion of the recess proximate the upper surface of the metal gate structure is narrower than a lower portion of the recess in the metal gate structure.

17 . A semiconductor device comprising:
a first fin over a substrate; a second fin over the substrate and adjacent to the first fin; a first metal gate over the first fin; a second metal gate over the second fin, wherein a first longitudinal direction of the first metal gate is along a same line as a second longitudinal direction of the second metal gate; and a dielectric structure disposed between and contacting the first metal gate and the second metal gate, the dielectric structure having an upper portion and a lower portion, the lower portion disposed between the upper portion and the substrate, wherein the lower portion extends beyond lateral extents of the upper portion along the first longitudinal direction.

18 . The semiconductor device of claim 17 , further comprising shallow trench isolation (STI) regions adjacent to the first fin and the second fin, wherein the lower portion of the dielectric structure contacts the STI regions.

19 . The semiconductor device of claim 17 , further comprising a dummy fin between the first fin and the second fin, wherein the lower portion of the dielectric structure contacts a top portion of the dummy fin.

20 . The semiconductor device of claim 17 , wherein the lower portion and the upper portion of the dielectric structure have a same width measured along a direction perpendicular to the first longitudinal direction.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hung Chih-Chang
• Feng Chieh-Ning
• Lai Chun-Liang
• Lin Yih-Ann
• Chen Ryan Chia-Jen

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H01L21/823437

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic

• H01L21/823481 Primary

  Electricity · mapped topic

• H01L29/6659

  Electricity · mapped topic