3D NAND memory device and method of forming the same

Patent metadata

Field	Value
Publication number	US-11145667-B2
Application number	US-201916367299-A
Country	US
Kind code	B2
Filing date	Mar 28, 2019
Priority date	Sep 13, 2018
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

In a memory device, a lower memory cell string is formed over a substrate to include a first channel structure, a plurality of first word line layers and first insulating layers. The first channel structure protrudes from the substrate and passes through the first word line layers and first insulating layers. An inter deck contact is formed over the lower memory cell string and connected with the first channel structure. An upper memory cell string is formed over the inter deck contact. The upper memory cell string includes a second channel structure, a plurality of second word lines and second insulating layers. The second channel structure passes through the second word lines and second insulating layers, and extends to the inter deck contact, and further extends laterally into the second insulating layers. A channel dielectric region of the second channel structure is above the inter deck contact.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
a substrate;
a lower deck formed over the substrate, the lower deck comprising a first channel structure that vertically extends from a surface of the substrate and a first memory cell stack that has a plurality of first layers and second layers, the first channel structure passing through the first memory cell stack and having sidewalls and a bottom portion, and the first layers and the second layers being alternatively stacked along the sidewalls of the first channel structure;
an inter deck contact formed over a top surface of the first memory cell stack and connected with the first channel structure; and
an upper deck formed over the inter deck contact, the upper deck comprising a second channel structure and a second memory cell stack, the second memory cell stack having a plurality of third layers and a plurality of fourth layers, the third layers and the fourth layers being alternatively stacked along sidewalls of the second channel structure, the second channel structure passing through the second memory cell stack and having sidewalls and a bottom portion, the second channel structure vertically extending into a recess in the inter deck contact and further extending laterally into the second memory cell stack at an interface of the inter deck contact, the second channel structure and the second memory cell stack, and the second channel structure having a channel dielectric region located above a top surface of the inter deck contact and a second channel layer, wherein:
the second channel layer extends through the second memory cell stack and extends into the inter deck contact,
the second channel layer includes (i) a bottom portion that extends into the inter deck contact, (ii) a top portion that has a tapered structure, and (iii) a middle portion that is positioned between the bottom portion and the top portion and adjacent to the interface, the middle portion having a rounded projection that extends away from the top surface of the inter deck contact, and extends outwards into the second memory cell stack, and
a top of the rounded projection in the middle portion is positioned above a bottom of the tapered structure in the top portion.

2. The device of claim 1 , wherein the channel dielectric region of the second channel structure comprises:
a second tunneling layer formed on the second channel layer and having a bottom surface;
a second charge storage layer formed on the second tunneling layer and having a bottom surface; and
a second blocking layer formed on the second charge storage layer, extending along the sidewalls of the second channel structure so as to be in contact with the second memory cell stack, and having a bottom surface,
wherein the second channel layer is in contact with an upper surface of the inter deck contact, a lowermost layer of the second memory cell stack, and the bottom surfaces of the second tunneling layer, second charge storage layer and second blocking layer.

3. The device of claim 1 , wherein a lower part of the sidewalls of the second channel structure below the top surface of the inter deck contact comprises a smaller number of layers than an upper part of the sidewalls of the second channel structure above the top surface of the inter deck contact.

4. The device of claim 2 , wherein:
the bottom surface of the second blocking layer is positioned above the top surface of the inter deck contact and disposed on the middle portion of the second channel layer at the interface;
the bottom surface of the second charge storage layer is positioned above the top surface of the inter deck contact and disposed on the middle portion of the second channel layer at the interface; and
the bottom surface of the second tunneling layer is positioned above the top surface of the inter deck contact and disposed on the middle portion of the second channel layer at the interface.

5. The device of claim 4 , wherein:
the second channel layer is formed over the second tunneling layer along the sidewalls of the second channel structure and extends into the inter deck contact;
a second dielectric layer formed over the second channel layer in the second channel structure, and extending into the inter deck contact; and
a top channel contact connected with the second channel layer, a top surface of the top channel contact being level with a top surface of the second memory cell stack.

6. The device of claim 1 , wherein the first channel structure and the second channel structure have a circular pillar-shape.

7. The device of claim 1 , wherein the first channel structure further comprises:
a first blocking layer formed along the sidewalls of the first channel structure and over the substrate, the first blocking layer being in contact with the first memory cell stack;
a first charge storage layer formed along the first blocking layer and over the substrate;
a first tunneling layer formed along the first charge storage layer and over the substrate;
a first channel layer formed along the first tunneling layer, the first channel layer being connected with the inter deck contact; and
a first dielectric layer formed along the first channel layer, the first dielectric layer filling the first channel structure and being in contact with the inter deck contact.

8. The device of claim 1 , wherein the first layers are first insulating layers and the second layers are first conductive layers, and a lowermost first layer of the first is in contact with the substrate.

9. The device of claim 8 , wherein each of the second layers comprises a first high K layer and a first metal layer to form a respective first word line.

10. The device of claim 1 , wherein the third layers are second insulating layers and the fourth layers are second conductive layers, and a lowermost third layer of the third layers is in contact with the inter deck contact.

11. The device of claim 10 , wherein each of the fourth layers comprises a second high K layer and a second metal layer to form a respective second word line.

12. A method for manufacturing a three-dimensional memory device, comprising:
forming a lower memory cell string over a substrate, the lower memory cell string including a plurality of first word lines sequentially stacked over the substrate, a plurality of first insulating layers and a first channel structure, the plurality of first word lines being spaced apart from each other by the plurality of first insulating layers, and the first channel structure passing through the plurality of first word lines and the plurality of first insulating layers, the first channel structure being formed along a direction perpendicular to the substrate, and coupled with the substrate via a bottom channel contact;
forming an interconnect structure over the lower memory cell string, the interconnect structure being connected with the first channel structure; and
forming an upper memory cell string over the interconnect structure, the upper memory cell string including a plurality of second word lines sequentially stacked over the interconnect structure, a plurality of second insulating layers and a second channel structure, the plurality of second word lines being spaced apart from each other by the plurality of second insulating layers, and the second channel structure passing through the plurality of second word lines and the plurality of second insulating layers, the second channel structure being formed along a direction perpendicular to the substrate, the second channel structure having sidewalls and a bottom portion, the second channel structure extending into the interconnect structure vertically and extendi

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Ruo Fang
• Wang Enbo
• Yang Haohao
• Xu Qianbing
• Hu Yushi
• Zhang Fushan

Classifications

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic