Method for fabricating semiconductor package and semiconductor package using the same

Patent metadata

Field	Value
Publication number	US-10468343-B2
Application number	US-201815874602-A
Country	US
Kind code	B2
Filing date	Jan 18, 2018
Priority date	Dec 8, 2015
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

First claim

The invention claimed is:

1. An electronic device comprising:
a substrate comprising:
a first molded encapsulant having a first side and a second side;
a first conductive pattern at the first side of the first molded encapsulant and embedded in the first side of the first molded encapsulant;
a second conductive pattern at the second side of the first molded encapsulant; and
a conductive path that ends through the first molded encapsulant and electrically connects the first conductive pattern to the second conductive pattern;

an electronic component mounted on the substrate and electrically connected to the first and second conductive patterns; and
a second molded encapsulant over the first molded encapsulant and at least laterally surrounding the electronic component,
wherein the first molded encapsulant comprises an aperture through which the first conductive pattern is exposed from the first molded encapsulant, the aperture comprising sidewalls that extend between the first side of the first molded encapsulant and the first conductive pattern.

2. The electronic device of claim 1 , wherein the first conductive pattern is completely embedded in the first molded encapsulant.

3. The electronic device of claim 1 , wherein the sidewalls surround the aperture.

4. The electronic device of claim 2 , comprising a conductive bump, at least a portion of which is positioned in the aperture.

5. The electronic device of claim 4 , wherein the conductive bump comprises solder.

6. The electronic device of claim 4 , wherein the substrate comprises:
a first contact at the first side of the first molded encapsulant and positioned laterally outside a footprint of the electronic component, wherein the first contact is connected to a first through-mold via;
a second contact at the first side of the first molded encapsulant and positioned laterally outside the footprint of the electronic component, wherein the second contact is connected to a second through-mold via; and
a third contact within the footprint of the electronic component and connected to a corresponding contact of the electronic component, wherein the third contact is directly between the first contact and the second contact.

7. The electronic device of claim 1 , wherein:
the conductive path comprises a first end at the first conductive pattern;
the conductive path comprises a second end at the second conductive pattern; and
the first end is narrower than the second end.

8. The electronic device of claim 1 , wherein the electronic component is mounted to the first side of the substrate.

9. The electronic device of claim 8 , wherein the electronic component comprises a contact that is soldered to the first conductive pattern.

10. The electronic device of claim 9 , wherein the first molded encapsulant comprises an aperture through which the contact is soldered to the first conductive pattern.

11. The electronic device of claim 1 , wherein the second conductive pattern is not embedded in the first molded encapsulant.

12. The electronic device of claim 1 , wherein the first molded encapsulant comprises a first lateral side surface, and the second molded encapsulant comprises a second lateral side surface that is coplanar with the first lateral side surface.

13. An electronic device comprising:
a substrate comprising:
a first molded encapsulant having a first side and a second side;
a first conductive pattern at the first side of the first molded encapsulant, wherein the first conductive pattern is exposed from the first molded encapsulant through an aperture in the first molded encapsulant, the aperture comprising side walls that extend between the first side of the first molded encapsulant and the first conductive pattern; and
a second conductive pattern at the second side of the first molded encapsulant;

a semiconductor die mounted on the substrate and electrically connected to the first and second conductive patterns;
a second molded encapsulant over the first molded encapsulant and at least laterally surrounding the semiconductor die; and
a solder bump attached to the first conductive pattern through the aperture.

14. The electronic device of claim 13 , wherein the semiconductor die comprises a contact that is attached to the solder bump.

15. The electronic device of claim 13 , comprising a mask layer through which the aperture extends.

16. The electronic device of claim 13 , wherein the solder bump completely fills the aperture.

17. A method of manufacturing an electronic device, the method comprising:
providing a substrate comprising:
a first molded encapsulant having a first side and a second side;
a first conductive pattern at the first side of the first molded encapsulant and embedded in the first side of the first molded encapsulant;
a second conductive pattern at the second side of the first molded encapsulant; and
a conductive path that ends through the first molded encapsulant and electrically connects the first conductive pattern to the second conductive pattern;

mounting an electronic component on the substrate, wherein the electronic component is electrically connected to the first and second conductive patterns; and
forming a second molded encapsulant over the first molded encapsulant and at least laterally surrounding the electronic component,
wherein the first molded encapsulant comprises an aperture through which the first conductive pattern is exposed.

18. The method of claim 17 , wherein the first conductive pattern is completely embedded in the first molded encapsulant.

19. The method of claim 17 , wherein the first molded encapsulant laterally surrounds the aperture.

20. The method of claim 17 , comprising a conductive bump, at least a portion of which is positioned in the aperture.

Assignees

• Amkor Technology Inc

Inventors

• Lee Seung Woo
• Kim Byong Jin
• Bang Won Bae
• Kang Sang Goo

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title