Nonvolatile memory apparatus for mitigating read disturbance and system using the same

Patent metadata

Field	Value
Publication number	US-11145364-B2
Application number	US-202016738945-A
Country	US
Kind code	B2
Filing date	Jan 9, 2020
Priority date	Jun 21, 2019
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

First claim

What is claimed is:

1. A nonvolatile memory apparatus comprising:
a memory cell coupled between a global bit line and a global word line;
a bit line control circuit configured to provide a first high voltage to the global bit line based on a read signal and to provide a second high voltage to the global bit line based on a first control signal;
a word line control circuit configured to provide a first low voltage to the global word line based on the read signal and to provide a second low voltage to the global word line based on a second control signal, and configured to control a first current to flow through the global word line based on the read signal and to control a second current to flow through the global word line based on the second control signal; and
a sense amplifier configured to sense snapback of the memory cell and generate the first and second control signals,
wherein the second current is larger than the first current, and the second current comprises an amount of current capable of setting the resistance state of the memory cell to a low resistance state.

2. The nonvolatile memory apparatus according to claim 1 , wherein the bit line control circuit provides the first high voltage to the global bit line based on the read signal, and provides the second high voltage having a higher voltage level than the first high voltage to the global bit line based on the first control signal.

3. The nonvolatile memory apparatus according to claim 1 , wherein the bit line control circuit comprises:
a read voltage supply circuit configured to generate the first high voltage by lowering the voltage level of a first read supply voltage, and supply the first high voltage to the global bit line, based on a clamping signal and a read enable signal generated from the read signal; and
a bypass circuit configured to generate the second high voltage from the first read supply voltage, and supply the second high voltage to the global bit line, based on the first control signal.

4. The nonvolatile memory apparatus according to claim 1 , wherein the bit line control circuit comprises:
a read voltage supply circuit configured to generate the first high voltage by lowering the voltage level of a first read supply voltage, and supply the first high voltage to the global bit line, based on a clamping signal and a read enable signal generated from the read signal; and
an anneal voltage supply circuit configured to generate the second high voltage from an anneal high voltage having a lower voltage level than the first read supply voltage, and supply the second high voltage to the global bit line, based on the first control signal.

5. The nonvolatile memory apparatus according to claim 1 , wherein the word line control circuit provides the first low voltage to the global word line based on the read signal, and provides the second low voltage having a lower voltage level than the first low voltage to the global word line based on the second control signal.

6. The nonvolatile memory apparatus according to claim 1 , wherein the word line control circuit controls the first current to flow through the global word line based on the read signal, and controls the second current to flow through the global word line based on the second control signal, wherein the second current is larger than the first current.

7. The nonvolatile memory apparatus according to claim 1 , wherein the word line control circuit comprises:
a read current circuit configured to supply a second read supply voltage as the first low voltage to the global word line, and control the first current to flow through the global word line, based on the read signal; and
an anneal current circuit configured to supply an anneal low voltage, which has a lower voltage level than the second read supply voltage, as the second low voltage to the global word line, and control the second current to flow through the global word line, based on the second control signal.

8. The nonvolatile memory apparatus according to claim 7 , wherein the read current circuit comprises:
a precharge circuit configured to supply the second read supply voltage to the global word line based on a precharge signal; and
a first current mirror comprising a first current source for supplying the first current, and configured to control the first current to flow through the global word line, when a read pulse signal generated from the read signal is enabled.

9. The nonvolatile memory apparatus according to claim 7 , wherein the anneal current circuit comprises a second current mirror comprising a second current source for supplying the second current, and configured to control the second current to flow through the global word line when the second control signal is enabled.

10. The nonvolatile memory apparatus according to claim 1 , wherein the sense amplifier generates the first and second control signals when the voltage level of the global word line is higher than the voltage level of a reference voltage.

11. The nonvolatile memory apparatus according to claim 1 , wherein the sense amplifier disables the second control signal before disabling the first control signal.

12. The nonvolatile memory apparatus according to claim 1 , wherein the memory cell is coupled between a bit line and a word line,
wherein the nonvolatile memory apparatus further comprises:
a column selection switch configured to couple the global bit line to the bit line based on a column selection signal;
a voltage level shifter configured to lower the voltage level of a row selection signal; and
a row selection switch configured to couple the global word line to the word line based on an output of the voltage level shifter.

13. An operation method of a nonvolatile memory apparatus, the method comprising:
selecting a bit line to couple a memory cell to a global bit line, and selecting a word line to couple the memory cell to a global word line;
applying a first high voltage to the global bit line and applying a first low voltage to the global word line, such that a first current flows through the memory cell, a voltage level difference between the first high voltage and the first low voltage corresponds to a voltage level of a read voltage;
sensing whether snapback of the memory cell occurred; and
applying a second high voltage to the global bit line and applying a second low voltage to the global word line, such that a second current flows through the memory cell, when the snapback of the memory cell occurred,
wherein the second current is larger than the first current, and the second current comprises an amount of current capable of setting the resistance state of the memory cell to a low resistance state.

14. The operation method according to claim 13 , wherein the second high voltage has a higher voltage level than the first high voltage.

15. The operation method according to claim 13 , wherein the second low voltage has a lower voltage level than the first low voltage.

16. The operation method according to claim 13 , wherein selecting the bit line to couple the memory cell to the global bit line comprises:
generating a column selection signal based on a column address signal; and
coupling the bit line to the global bit line based on the column selection signal.

17. The operation method according to claim 16 , wherein selecting the word line to couple the memory cell to the global word line comprises:
generating a row selection signal based on a row address signal;
lowering the voltage level of the row selection signal; and
coupling the word line to the global word line

Assignees

• Sk Hynix Inc

Inventors

• Park Moo Hui
• Kang Seok Joon
• Cheon Jun Ho

Classifications

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C13/003

  Cell access · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title