Component carrier with high passive intermodulation performance

Patent metadata

Field	Value
Publication number	US-11140768-B2
Application number	US-202016841394-A
Country	US
Kind code	B2
Filing date	Apr 6, 2020
Priority date	Apr 10, 2019
Publication date	Oct 5, 2021
Grant date	Oct 5, 2021

Abstract

A component carrier which includes a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure, and electrically conductive wiring structures being part of the at least one electrically conductive layer structure, wherein a value of the passive intermodulation for signals propagating along the electrically conductive wiring structures is less than −153 dBc.

First claim

The invention claimed is:

1. A component carrier, comprising:
a stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure;
electrically conductive wiring structures being part of the at least one electrically conductive layer structure;
wherein a roughness of a horizontal surface of the electrically conductive wiring structures has an impact on a value of a passive intermodulation for signals propagating along the electrically conductive wiring structures, wherein the roughness of a horizontal surface of the electrically conductive wiring structures is less than 300 nm so that the value of the passive intermodulation is less than −153 dBc;
wherein the electrically conductive wiring structures include an electrically conductive base structure and a plated structure on the base structure;
wherein a surface of the electrically conductive base structure below the plated structure has a roughness Rz of less than 1.6 μm.

2. The component carrier according to claim 1 , wherein the value of the passive intermodulation is less than −155 dBc.

3. The component carrier according to claim 1 , comprising at least one of the following features:
wherein an entire surface of a plated structure of the electrically conductive wiring structures has a roughness Rz of less than 300 nm.

4. The component carrier according to claim 1 , comprising at least one of the following features:
wherein a surface finish covering at least part of the electrically conductive wiring structures, wherein the surface finish comprises or consists of tin;
wherein at least part of a surface of the electrically conductive wiring structures is covered with an adhesion promoter;
wherein at least one electronic component mounted on or embedded in the stack and being electrically coupled with the electrically conductive wiring structures;
wherein the stack includes a central electrically insulating layer structure covered on both opposing main surfaces thereof with a respective electrically conductive layer structure;
wherein the stack includes at least one through hole extending vertically through the at least one electrically insulating layer structure and being at least partially filled with an electrically conductive filling medium for electrically connecting electrically conductive wiring structures on both opposing main surfaces of the at least one electrically insulating layer structure.

5. The component carrier according to claim 1 , comprising at least one of the following features:
wherein the base structure is a patterned metal foil;
wherein the base structure has a thickness in a range between 5 μm and 30 μm;
wherein the plated structure is a plated copper structure;
wherein the plated structure comprises at least two stacked plating layers;
wherein the plated structure has a thickness in a range between 20 μm and 70 μm.

6. The component carrier according to claim 1 , comprising at least one of the following features:
wherein the electrically conductive wiring structures form an antenna structure;
wherein at least one component being surface mounted on or embedded in the component carrier, wherein the at least one component is selected from a group consisting of an electronic component, an electrically non-conductive or electrically conductive inlay, a heat transfer unit, a light guiding element, an energy harvesting unit, an active electronic component, a passive electronic component, an electronic chip, a storage device, a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a voltage converter, a cryptographic component, a transmitter or receiver, an electromechanical transducer, an actuator, a microelectromechanical system, a microprocessor, a capacitor, a resistor, an inductance, an accumulator, a switch, a camera, an antenna, a magnetic element, a further component carrier, and a logic chip;
wherein the at least one electrically conductive layer structure comprises at least one of a group consisting of copper, aluminum, nickel, silver, gold, palladium, and tungsten, any of the mentioned materials being optionally coated with supra-conductive material such as graphene;
wherein the at least one electrically insulating layer structure comprises at least one of the group consisting of resin, epoxy resin, Bismaleimide-Triazine resin, FR-4, FR-5, cyanate ester, polyphenylene derivate, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based build-up material, polytetrafluoroethylene, a ceramic, and a metal oxide;
wherein the component carrier is shaped as a plate;
wherein the component carrier is configured as one of a group consisting of a printed circuit board, and a substrate;
wherein the component carrier is configured as a laminate-type component carrier.

7. A method of manufacturing a component carrier, comprising:
forming a stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure; and
forming electrically conductive wiring structures being part of the at least one electrically conductive layer structure;
wherein a roughness of a horizontal surface of the electrically conductive wiring structures has an impact on a value of a passive intermodulation for signals propagating along the electrically conductive wiring structures, wherein the roughness of a horizontal surface of the electrically conductive wiring structures is less than 300 nm so that the value of passive intermodulation is less than −153 dBc;
wherein the electrically conductive wiring structures include an electrically conductive base structure and a plated structure on the base structure;
wherein a surface of the electrically conductive base structure below the plated structure has a roughness Rz of less than 1.6 μm.

8. The method according to claim 7 , comprising at least one of the following features:
wherein the method includes attaching a metal foil as the base structure or as a preform of the base structure to the at least one electrically insulating layer structure;
wherein the method includes plating electrically conductive material as the plated structure or as a preform of the plated structure on the base structure or on a preform of the base structure.

9. The method according to claim 7 , wherein the method includes forming the plated structure with a first plating layer on the base structure and with a second plating layer on the first plating layer, wherein the first plating layer and the second plating layer are formed in separate plating procedures.

10. The method according to claim 9 , comprising at least one of the following features:
wherein the method includes plating the first plating layer on the base structure before applying an etch resist, and plating the second plating layer on only a part of the first plating layer after applying the etch resist, wherein the method includes commonly removing a part of the first plating layer and a part of the base structure by etching after applying the etch resist, wherein the method includes applying an etch protection to the second plating layer before the etching;
wherein the method includes forming the first plating layer by flash plating.

11. A method, comprising:
providing a component carrier with a stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure, electrically conductive wiring structures being part of the at least one electrically conductive layer structure, wherein a roughness of a horizontal surface of the electrically conductive wiring structures

Assignees

• At & S Austria Tech & Systemtechnik Ag

Inventors

• Pöltl Kevin
• Oberegger Rene
• Klaus Konrad
• Schlaffer Erich

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title