Package substrate having photo-sensitive dielectric layer and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9485874-B2
Application number	US-201314010250-A
Country	US
Kind code	B2
Filing date	Aug 26, 2013
Priority date	Oct 11, 2012
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A package substrate and a method of fabricating the package substrate are provided. The package substrate may include an interposer having at least one conductive through via, a photo-sensitive dielectric layer formed on one side of the interposer, and at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via. By means of a photo lithography process with high alignment accuracy, at least one via with an extremely small diameter can be formed on the photo-sensitive dielectric layer and align with the conductive through via. Therefore, the conductive through via can have its diameter reduced as required, without considering the alignment with the at least one via. Accordingly, the interconnection density of the conductive through via on the interposer is increased.

First claim

What is claimed is:

1. A package substrate, comprising:
an interposer having a first side and a second side opposite to the first side;
at least one conductive through via penetrating from the first side to the second side;
a redistribution layer formed on the first side and electrically connected to the conductive through via;
a photo-sensitive dielectric layer formed on the second side of the interposer;
a molding layer formed to encapsulate the interposer, wherein a bottom surface of the molding layer is aligned with an end of the conductive through via, and the photo-sensitive dielectric layer directly covers the molding layer and the interposer; and
at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via, wherein the conductive via is in direct physical and electrical contact with the conductive through via,
wherein the photo-sensitive dielectric layer is photo-sensitive polyimide (PSPI).

2. The package substrate of claim 1 , wherein the interposer contains silicon.

3. The package substrate of claim 2 , wherein the conductive via is free of electrical contact with the silicon of the interposer.

4. The package substrate of claim 1 , further comprising an insulation layer formed on a sidewall of the conductive through via, between the conductive through via and a material of the interposer.

5. The package substrate of claim 1 , further comprising a circuit layer formed on or in the photo-sensitive dielectric layer and electrically connected to the conductive via.

6. The package substrate of claim 1 , further comprising a circuit layer, wherein
the conductive through via has opposite first and second ends, the first end on the first side, and the second end on the second side,
the conductive via has opposite first and second ends, the first end of the conductive via in direct physical and electrical contact with the second end of the conductive through via, and
the circuit layer is in direct physical and electrical contact with the second end of the conductive via, has a width greater than a diameter of the conductive through via.

7. The package substrate of claim 5 , further comprising:
a circuit built-up structure disposed on the photo-sensitive dielectric layer and the circuit layer; and
an insulating protection layer formed on the circuit built-up structure and having at least one opening exposing a portion of the circuit built-up structure that defines a conductive pad, wherein the molding layer encapsulates the interposer on at least two opposite lateral sides, and a bottom side of the molding layer is coplanar with the second side of the interposer.

8. The package substrate of claim 7 , wherein the photo-sensitive dielectric layer and the circuit built-up structure extend under the bottom side of the molding layer.

9. The package substrate of claim 1 , wherein a location shift of the conductive via relative to the conductive through via is less than 10 μm.

10. A method of fabricating a package substrate, comprising:
providing a plurality of interposers, wherein each interposer has
a first side and a second side opposite to the first side,
at least one conductive through via penetrating from the first side to the second side, and
a top redistribution layer formed on the first side of the interposer and electrically connected to a top end of the conductive through via;
molding for encapsulating the plurality of interposers, wherein the molding has a bottom side coplanar with the second side of each interposer;
forming a photo-sensitive dielectric layer on the second side of the plurality of interposers and under the bottom side of the molding;
forming, in the photo-sensitive dielectric layer, at least one via for the conductive through via to be exposed therefrom; and
forming a conductive via in the via for the conductive via to be electrically connected to the conductive through via,
wherein the at least one via is formed in the photo-sensitive dielectric layer by performing a photo lithography process on the photo-sensitive dielectric layer.

11. The method of claim 10 , wherein each interposer contains silicon.

12. The method of claim 11 , wherein the conductive via is formed to be free of electrical contact with the silicon of each interposer.

13. The method of claim 10 , further comprising:
forming an insulation layer on a sidewall of the conductive through via, between the conductive through via and the interposer in which the conductive through via is formed.

14. The method of claim 10 , further comprising forming, on or in the photo-sensitive dielectric layer, a circuit layer electrically connected to a bottom end of the conductive via, wherein
the conductive through via has opposite first and second ends, the first end on the first side, and the second end on the second side,
the conductive via has opposite first and second ends, the first end of the conductive via is formed to be in direct physical and electrical contact with the second end of the conductive through via, and
the circuit layer is formed to be in direct physical and electrical contact with the second end of the conductive via.

15. The method of claim 14 , further comprising:
forming a circuit built-up structure on a bottom side of the photo-sensitive dielectric layer;
wherein the photo-sensitive dielectric layer and the circuit built-up structure extend under the bottom side of the molding.

16. The method of claim 15 , further comprising:
forming on the circuit built-up structure, an insulating protection layer having a plurality of openings for exposing a portion of the circuit built-up structure that defined a conductive pad.

17. The method of claim 10 , wherein the photo lithography process is performed on the photo-sensitive dielectric layer so that a location shift of the conductive via relative to the conductive through via is less than 10 μm.

18. The method of claim 10 , wherein the photo-sensitive dielectric layer is photo-sensitive polyimide (PSPI).

19. The method of claim 10 , further comprising
a cutting process, to cut through a middle of the molding to yield a plurality of individual package units.

Assignees

• Ind Tech Res Inst
• Unimicron Technology Corp
• Unimicron Technology Corp

Inventors

• Chen Yu-Hua
• Lo Wei-Chung
• Hu Dyi-Chung
• Hsieh Chang-Hong

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/698 Primary

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title