Superconducting bump bonds

Patent metadata

Field	Value
Publication number	US-11133450-B2
Application number	US-201916557378-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Dec 15, 2015
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.

First claim

What is claimed is:

1. A method comprising:
providing a first chip comprising a first circuit element;
forming a first aluminum interconnect pad on a first surface of the first chip so that the first aluminum interconnect pad is electrically connected to the first circuit element;
forming a first titanium nitride barrier layer on the first aluminum interconnect pad;
providing a second chip comprising a second circuit element;
forming a bump bond consisting of indium; and
joining the first chip to the second chip with the indium bump bond so that the first circuit element is electrically connected to the second circuit element.

2. The method of claim 1 , further comprising removing a native oxide from the first aluminum interconnect pad prior to forming the first titanium nitride barrier layer.

3. The method of claim 2 , wherein removing the native oxide comprises ion milling a surface of the first aluminum interconnect pad.

4. The method of claim 1 , wherein forming the first titanium nitride barrier comprises reactive sputtering titanium nitride on the first aluminum interconnect pad.

5. The method of claim 1 , further comprising ion milling a surface of the first titanium nitride barrier layer prior to joining the first chip to the second chip.

6. The method of claim 1 , further comprising exposing a surface of the bump bond to a H 2 plasma.

7. The method of claim 1 , further comprising:
forming a second aluminum interconnect pad on a first surface of the second chip so that the second aluminum interconnect pad is electrically connected to the second circuit element; and
forming a second titanium nitride barrier layer on the second aluminum interconnect pad of the second chip.

8. The method of claim 7 , further comprising removing a native oxide from the second aluminum interconnect pad of the second chip prior to forming the second titanium nitride barrier layer.

9. The method of claim 8 , wherein removing the native oxide from the second aluminum interconnect pad comprises ion milling a surface of the second aluminum interconnect pad.

10. The method of claim 7 , wherein forming the second titanium nitride barrier layer on the second aluminum interconnect pad comprises reactive sputtering titanium nitride on the second aluminum interconnect pad.

11. The method of claim 7 , further comprising ion milling a surface of the second titanium nitride barrier layer prior to joining the first chip to the second chip.

12. The method of claim 7 , wherein forming the bump bond comprises depositing indium on the first titanium nitride barrier, on the second titanium nitride barrier, or on both the first and second titanium nitride barriers.

13. The method of claim 1 , wherein the first circuit element comprises a rapid single flux quantum (RSFQ) device and the second circuit element comprises a quantum circuit element.

14. The method of claim 1 , wherein the first circuit element comprises first quantum circuit element and the second circuit element comprises a second quantum circuit element.

Assignees

• Google Llc

Inventors

• Mutus Joshua Yousouf
• Lucero Erik Anthony

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07232

  Compression bonding, e.g. thermocompression bonding · CPC title

• H10W72/01971

  Cleaning, e.g. oxide removal · CPC title