Metal-based passivation-assisted plasma etching of III-v semiconductors

Patent metadata

Field	Value
Publication number	US-11133190-B2
Application number	US-201815971999-A
Country	US
Kind code	B2
Filing date	May 4, 2018
Priority date	May 5, 2017
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

According to one embodiment, a method includes performing a plasma etching process on a masked III-V semiconductor, and forming a passivation layer on etched portions of the III-V semiconductor. The passivation layer includes at least one of a group III element and/or a metal from the following: Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.

First claim

What is claimed is:

1. A structure, comprising:
a III-V semiconductor having etched portions comprising a sidewall and a bottom; and
a passivation layer on the etched portions of the III-V semiconductor, the passivation layer comprising a group III element and/or a metal selected from the group consisting of Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc,
wherein the passivation layer is present on the sidewall and the bottom,
wherein the passivation layer is less present on the bottom than the sidewall, and wherein a thickness of the passivation layer is less than 500 nanometers.

2. The structure of claim 1 , wherein the passivation layer comprises aluminum.

3. The structure of claim 1 , wherein the passivation layer is electrically conductive.

4. The structure of claim 1 , wherein the passivation layer is electrically insulative.

5. The structure of claim 1 , wherein the passivation layer is semiconducting.

6. The structure of claim 1 , wherein the passivation layer includes aluminum oxide.

7. The structure of claim 1 , wherein the III-V semiconductor has a single composition.

8. The structure of claim 1 , wherein the structure is an array of pillars, wherein each pillar has an average aspect ratio in a range of 1.5:1 to about 6:1, wherein each etched portion is between each pillar and an adjacent pillar, wherein the sidewall is oriented vertically and the bottom is oriented horizontally.

9. The structure of claim 1 , wherein the sidewall is oriented perpendicular to the bottom, wherein each nonetched portion is a pillar having an average aspect ratio (height to width) greater than 2.5:1.

10. A method for forming the structure of claim 1 , the method comprising:
performing a plasma etching process on a masked III-V semiconductor, wherein the plasma etching process forms a pillar of III-V semiconductor having an average aspect ratio in a range of 1:1 to 6:1; and
forming the passivation layer on etched portions of the III-V semiconductor, the passivation layer comprising at least one of the group III element and/or the metal selected from the group consisting of Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.

11. The method of claim 10 , wherein the passivation layer comprises a material selected from the group consisting of: elemental aluminum, an aluminum nitride, an aluminum silicate, an aluminum halide, an aluminum alloy, and aluminum gallium nitride.

12. The method of claim 10 , wherein the passivation layer is formed concurrently with the plasma etching process.

13. The method of claim 10 , wherein the passivation layer is formed between periods of the plasma etching process.

14. The method of claim 10 , comprising applying an additive gas to a vicinity of the III-V semiconductor for altering a composition of a material being deposited to form the passivation layer.

15. The method of claim 10 , wherein forming the passivation layer includes applying a passivation gas to a vicinity of the III-V semiconductor, the passivation gas including a material being deposited to form the passivation layer.

16. The method of claim 10 , wherein the passivation layer remains on the etched portions of the III-V semiconductor after plasma etching process is completed, wherein the passivation layer is a part of a final semiconductor device structure.

17. The method of claim 10 , comprising removing the passivation layer from the III-V semiconductor after completion of the plasma etching process.

18. The method of claim 10 , wherein the average aspect ratio greater than 2.5:1.

19. The method of claim 10 , wherein the III-V semiconductor is masked by a mask, wherein a passivation material being deposited to form the passivation layer reacts with the mask thereby increasing a resistance of the mask to plasma etching.

20. The method of claim 19 , comprising actively promoting the reaction of the passivation material with the mask.

Assignees

• L Livermore Nat Security Llc

Inventors

• Harrison Sara E
• Frye Clint
• Nikolic Rebecca J
• Shao Qinghui
• Voss Lars F

Classifications

• H10P70/20

  Cleaning during device manufacture · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title