Three dimensional vertically structured electronic devices

Patent metadata

Field	Value
Publication number	US-2017200820-A1
Application number	US-201614990612-A
Country	US
Kind code	A1
Filing date	Jan 7, 2016
Priority date	Jan 7, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

First claim

1 . An apparatus, comprising:
at least one vertical transistor, comprising:
a substrate comprising a semiconductor material;
an array of three dimensional (3D) structures above the substrate, wherein each 3D structure comprises the semiconductor material, wherein each 3D structure comprises a first region having a first conductivity type wherein the first conductivity type corresponds to an n-type conductivity, and a second region having a second conductivity type wherein the second conductivity type corresponds to a p-type conductivity, the second region including a portion of at least one vertical sidewall of the 3D structure;
an isolation region positioned between the 3D structures; and
a gate region positioned along a portion of at least one vertical sidewall of each 3D structure.

2 . (canceled)

3 . The apparatus as recited in claim 1 , wherein the first conductivity type corresponds to a p-type conductivity, and the second conductivity type corresponds to a n-type conductivity.

4 . The apparatus as recited in claim 1 , wherein the semiconductor material is selected from the group consisting of: silicon, silicon carbide, a binary III-V semiconductor material, a ternary III-V semiconductor material, a quaternary III-V semiconductor material, and combinations thereof.

5 . The apparatus as recited in claim 1 , wherein the semiconductor material comprises GaN.

6 . The apparatus as recited in claim 1 , wherein a total height of each 3D structure is in a range from about 0.1 μm to about 1000 μm.

7 . The apparatus as recited in claim 6 , wherein a height of the second region of each 3D structure is in a range from greater than 0% to less than or equal to about 100% of the total height of the 3D structure.

8 . The apparatus as recited in claim 6 , wherein the first region of each 3D structure comprises a lower region (a drift region) positioned between the second region and an upper surface of the substrate in a vertical direction, the vertical direction being oriented perpendicular to the upper surface of the substrate, and wherein a height of the lower region is in a range from greater than 0% to less than or equal to about 50% of the total height of the 3D structure.

9 . The apparatus as recited in claim 1 , wherein a total width of each 3D structure is in a range from about 0.001 μm to about 100 μm.

10 . The apparatus as recited in claim 9 , wherein a width of the second region of each 3D structure is in a range from about 10% to about 20% of the total width of the 3D structure.

11 . The apparatus as recited in claim 1 , wherein the isolation region comprises at least one of: a polymeric material, glass, SiNx, SiO 2 , Al 2 O 3 , Ga 2 O 3 , MgO, Y 2 O 3 , Gd 2 O 3 , air, and combinations thereof.

12 . The apparatus as recited in claim 1 , wherein the vertical transistor comprises:
a source region coupled to an upper surface of each 3D structure, a drain region coupled to a lower surface of the substrate; and wherein the gate regions are positioned above the isolation region.

13 . The apparatus as recited in claim 12 , wherein the first region of each 3D structure comprises an upper region positioned above the second region, the upper region being configured to isolate the source and gate regions.

14 . The apparatus as recited in claim 13 , wherein a portion of the upper region of each 3D structure extends above the second region, and wherein the gate region of each 3D structure is coupled to the portion of at least one vertical sidewall of the 3D structure that includes the second region.

15 . The apparatus as recited in claim 13 , wherein the upper region of each 3D structure does not extend above the second region, and wherein the gate region of each 3D structure is positioned above and coupled to an upper surface of the second region, and is coupled to a portion of the vertical sidewall of the 3D structure that includes the upper region.

16 . A method of forming the vertical transistor of claim 1 , comprising:
forming a layer comprising the semiconductor material above the substrate; defining the 3D structures in the layer; forming the second region in at least one vertical sidewall of each 3D structure; and forming the isolation region between the 3D structures.

17 . The method as recited in claim 16 , wherein the 3D structures are defined via an etching technique and/or an ion implantation technique.

18 . An apparatus, comprising:
at least one vertical transistor, comprising:
a substrate comprising a first semiconductor material;
an array of three dimensional (3D) structures above the substrate, wherein each 3D structure comprises the first semiconductor material;
a first sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, wherein the first sidewall heterojunction layer comprises a second semiconductor material, wherein the first and second semiconductor materials have different bandgaps; and
an isolation region positioned between the 3D structures.

19 . The apparatus as recited in claim 18 , wherein the first semiconductor material comprises GaN, and wherein the second semiconductor material comprises at least one of: Al x Ga 1-x N, wherein 0≦x≦1; and In y Ga 1-y N, wherein 0≦y≦1.

20 . The apparatus as recited in claim 18 , wherein the vertical transistor comprises:
a source region coupled to an upper surface of each 3D structure; a first gate region positioned above the isolation region and coupled to a vertical sidewall of the first sidewall heterojunction layer of each 3D structure; and a drain region coupled to a lower surface of the substrate.

21 . The apparatus as recited in claim 20 , wherein the vertical transistor comprises a second sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, the second sidewall heterojunction layer comprising a third semiconductor material, wherein the first and third semiconductor materials have different bandgaps.

22 . The apparatus as recited in claim 21 , wherein the second semiconductor material and the third semiconductor material are the same.

23 . The apparatus as recited in claim 21 , wherein the second semiconductor material and the third semiconductor material are different.

24 . The apparatus as recited in claim 21 , wherein the second semiconductor material and the third semiconductor material each independently comprise at least one of: Al x Ga 1-x N, wherein 0≦x≦1; and In y Ga 1-y N, wherein 0≦y≦1.

25 . The apparatus as recited in claim 21 , wherein the vertical transistor comprises a second gate region positioned above the isolation region and coupled to a vertical sidewall of the second sidewall heterojunction layer of each 3D structure.

26 . An apparatus, comprising:
at least one vertical transistor, comprising:
a substrate comprising a first semiconductor material;
at least one three dimensional (3D) structure above the substrate, wherein the 3D structure comprises the first semiconductor material;
a heterojunction capping layer above an upper surface of the 3D structure, the heterojunction capping layer comprising a second semiconductor material, wherein the first and second semiconductor materials have a different bandgap; and
a passivation layer positioned on at least one vertical sidewall of the 3D structure.

27 . The apparatus as recited in claim 26 , wherei

Assignees

• L Livermore Nat Security Llc

Inventors

• Conway Adam
• Harrison Sara Elizabeth
• Nikolic Rebecca
• Shao Qinghui
• Voss Lars

Classifications

• H10D30/485

  Vertical FETs having two-dimensional material channels · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824 Primary

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H01L29/205

  Electricity · mapped topic

• H01L29/7787

  Electricity · mapped topic