Electronic Devices Including A III-V Transistor Having A Homostructure And A Process Of Forming The Same
US-2016308045-A1 · Oct 20, 2016 · US
Three dimensional vertically structured misfet/mesfet
US2017200833A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017200833-A1 |
| Application number | US-201614990561-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jan 7, 2016 |
| Priority date | Jan 7, 2016 |
| Publication date | Jul 13, 2017 |
| Grant date | — |
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Abstract
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According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.
First claim
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1 . An apparatus, comprising: a substrate comprising a semiconductor material; and at least one three dimensional (3D) structure above the substrate, wherein the 3D structure comprises the semiconductor material, and wherein the 3D structure comprises: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure. 2 . The apparatus as recited in claim 1 , wherein the first conductivity type corresponds to an n-type conductivity or a p-type conductivity. 3 . The apparatus as recited in claim 1 , wherein the semiconductor material is selected from the group consisting of: silicon, silicon carbide, a binary III-V semiconductor material, a ternary III-V semiconductor material, a quaternary III-V semiconductor material, and combinations thereof. 4 . The apparatus as recited in claim 1 , wherein the semiconductor material comprises GaN. 5 . The apparatus as recited in claim 1 , wherein a total height of the 3D structure is in a range from about 0.1 μm to about 1000 μm. 6 . The apparatus as recited in claim 1 , wherein a total width of the 3D structure is in a range from about 0.001 μm to about 100 μm. 7 . The apparatus as recited in claim 1 , wherein the 3D structure is a pillar. 8 . The apparatus as recited in claim 1 , wherein the second region comprises one or more Schottky metal layers. 9 . The apparatus as recited in claim 8 , wherein a total height of the second region is in a range from greater than 0% to less than or equal to 100% of the total height of the 3D structure. 10 . The apparatus as recited in claim 9 , comprising an isolation region below the second region. 11 . The apparatus as recited in claim 10 , wherein the isolation region comprises at least one of: a polymeric material, glass, SiNx, SiO 2 , Al 2 O 3 , Ga 2 O 3 , MgO, Y 2 O 3 , Gd 2 O 3 , air, and combinations thereof. 12 . The apparatus as recited in claim 1 , comprising an array of 3D structures, wherein each 3D structure comprises the semiconductor material, and wherein each 3D structure comprises: the first region having the first conductivity type, and the second region coupled to a portion of at least one vertical sidewall of the 3D structure. 13 . The apparatus as recited in claim 1 , comprising: a source region coupled to an upper surface of the 3D structure; and a drain region coupled to a lower surface of the substrate. 14 . The apparatus as recited in claim 1 , wherein the second region comprises one or more insulating barrier layers. 15 . The apparatus as recited in claim 14 , wherein each insulating barrier layer individually comprises at least one of: a polymeric material, glass, SiNx, SiO 2 , Al 2 O 3 , Ga 2 O 3 , MgO, Y 2 O 3 , Gd 2 O 3 , air, and combinations thereof. 16 . The apparatus as recited in claim 14 , wherein a total height of the second region is in a range from greater than 0% to less than or equal to 100% of the total height of the 3D structure. 17 . The apparatus as recited in claim 16 , comprising a gate region coupled to a portion of the second region. 18 . The apparatus as recited in claim 17 , wherein a total height of the gate region is in a range from greater than 0% to less than or equal to 100% of the total height of the second region. 19 . The apparatus as recited in claim 18 , comprising an isolation region below the gate region. 20 . The apparatus as recited in claim 19 , wherein the isolation region comprises at least one of: a polymeric material, glass, SiNx, SiO 2 , Al 2 O 3 , Ga 2 O 3 , MgO, Y 2 O 3 , Gd 2 O 3 , air, and combinations thereof.
Assignees
Inventors
Classifications
Electricity · mapped topic
- H01L29/8083Primary
Electricity · mapped topic
Electricity · mapped topic
Orientations of crystalline planes · CPC title
Nitride Group III-V materials, e.g. AlN or GaN · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2017200833A1 cover?
- According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.
- Who is the assignee on this patent?
- L Livermore Nat Security Llc, Univ California
- What technology area does this patent fall under?
- Primary CPC classification H01L29/8083. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jul 13 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).