Shift register unit comprising input circuit, output circuit, and first node control circuit, gate driving circuit, display device, and driving method

Patent metadata

Field	Value
Publication number	US-11132934-B2
Application number	US-201916641737-A
Country	US
Kind code	B2
Filing date	Aug 16, 2019
Priority date	Sep 6, 2018
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, an output circuit, and a first node control circuit. The input circuit is configured to charge a first node in response to an input signal; the output circuit is configured to output an output signal at an output terminal under control of a level signal of the first node; and the first node control circuit is configured to receive a precharge control signal from a precharge control terminal and charge the first node in response to the precharge control signal before the output terminal outputs the output signal.

First claim

What is claimed is:

1. A shift register unit, comprising an input circuit, an output circuit, a first node control circuit, and an output control circuit,
wherein the input circuit is configured to charge a first node in response to an input signal;
the output circuit is configured to output an output signal at an output terminal under control of a level signal of the first node; and
the first node control circuit is configured to receive a precharge control signal from a precharge control terminal and charge the first node in response to the precharge control signal before the output terminal outputs the output signal,
the output control circuit is connected to the output terminal and the precharge control terminal, and is configured to receive the precharge control signal from the precharge control terminal and to control the output terminal to be at an invalid output level during a non-output phase in response to the precharge control signal.

2. The shift register unit according to claim 1 , wherein the input circuit is connected to the first node, the output circuit comprises the output terminal, and the output circuit is connected to the first node, and the first node control circuit is connected to the first node and the precharge control terminal.

3. The shift register unit according to claim 1 , wherein the first node control circuit comprises a first capacitor,
a first electrode of the first capacitor is connected to the first node, and a second electrode of the first capacitor is connected to the precharge control terminal to receive the precharge control signal.

4. The shift register unit according to claim 1 , wherein the output control circuit comprises a first transistor,
a gate electrode of the first transistor is connected to the precharge control terminal to receive the precharge control signal, a first electrode of the first transistor is connected to the output terminal, and a second electrode of the first transistor is connected to a first voltage terminal to receive a first voltage.

5. The shift register unit according to claim 1 , further comprising a first node reset circuit,
wherein the first node reset circuit is connected to the first node and configured to reset the first node in response to a reset signal.

6. The shift register unit according to claim 1 , further comprising a second node control circuit, a first node noise reduction circuit, and an output noise reduction circuit,
wherein the second node control circuit is connected to the first node and a second node, and is configured to control a level of the second node under control of the level signal of the first node;
the first node noise reduction circuit is connected to the first node and the second node, and is configured to perform noise reduction on the first node under control of a level signal of the second node; and
the output noise reduction circuit is connected to the second node and the output terminal, and is configured to perform noise reduction on the output terminal under control of the level signal of the second node.

7. The shift register unit according to claim 1 , wherein the output terminal comprises a shift output terminal and at least one scan signal output terminal.

8. The shift register unit according to claim 7 , wherein the at least one scan signal output terminal comprises one scan signal output terminal, the output circuit comprises a second transistor, a third transistor, and a second capacitor;
a gate electrode of the second transistor is connected to the first node, a first electrode of the second transistor is connected to a clock signal terminal to receive a clock signal, a second electrode of the second transistor is connected to the shift output terminal;
a gate electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the clock signal terminal to receive the clock signal, and a second electrode of the third transistor is connected to the scan signal output terminal;
a first electrode of the second capacitor is connected to the first node, and a second electrode of the second capacitor is connected to the scan signal output terminal or the shift output terminal; and
the clock signal is transmitted to the output terminal and serves as the output signal.

9. The shift register unit according to claim 1 , further comprising: a first node reset circuit, a total reset circuit, a second node control circuit, a first node noise reduction circuit, and an output noise reduction circuit;
wherein the first node reset circuit is connected to the first node and is configured to reset the first node in response to a reset signal;
the total reset circuit is connected to the first node and is configured to reset the first node in response to a total reset signal;
the second node control circuit is connected to the first node, a second node, and a third node, and is configured to control a level of the second node and a level of the third node under control of the level signal of the first node;
the first node noise reduction circuit is connected to the first node and the second node, and is configured to perform noise reduction on the first node under control of a level signal of the second node;
the output noise reduction circuit is connected to the second node and the output terminal, and is configured to perform noise reduction on the output terminal under control of the level signal of the second node;
the first node control circuit comprises:
a first capacitor, wherein a first electrode of the first capacitor is connected to the first node, and a second electrode of the first capacitor is connected to the precharge control terminal to receive the precharge control signal;
the output control circuit comprises:
a first transistor, wherein a gate electrode of the first transistor is connected to the precharge control terminal to receive the precharge control signal, a first electrode of the first transistor is connected to the output terminal, and a second electrode of the first transistor is connected to a first voltage terminal to receive a first voltage;
in a case where the output terminal comprises a shift output terminal and one scan signal output terminal, the output circuit comprises a second transistor, a third transistor, and a second capacitor,
a gate electrode of the second transistor is connected to the first node, a first electrode of the second transistor is connected to a clock signal terminal to receive a clock signal, a second electrode of the second transistor is connected to the shift output terminal;
a gate electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the clock signal terminal to receive the clock signal, and a second electrode of the third transistor is connected to the scan signal output terminal;
a first electrode of the second capacitor is connected to the first node, and a second electrode of the second capacitor is connected to the scan signal output terminal or the shift output terminal;
the clock signal is transmitted to the output terminal and serves as the output signal,
the input circuit comprises:
a fourth transistor, wherein a gate electrode and a first electrode of the fourth transistor are electrically connected to each other, and are configured to be both connected to an input terminal to receive the input signal, and a second electrode of the fourth transistor is configured to be connected to the first node;
the first node reset circuit comprises:
a fifth transistor, wherein a gate electrode of the fifth transistor is configured to be connected to a reset terminal to receive the reset signal, a first electrode of the fi

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Xie Yongxian
• Liu Jinliang
• Wang Hui
• Zhang Miao

Classifications

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G2230/00

  Details of flat display driving waveforms · CPC title