Shift register and display apparatus

Patent metadata

Field	Value
Publication number	US-10096372-B2
Application number	US-201615176151-A
Country	US
Kind code	B2
Filing date	Jun 8, 2016
Priority date	Jun 11, 2015
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A shift register and a display apparatus are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives a pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The duty cycle of the clock signal is less than 50 percent.

First claim

What is claimed is:

1. A shift register, comprising:
a pre-charge unit configured to receive a first input signal and a second input signal and to output a pre-charge signal via a first node based on the first input signal and the second input signal, wherein the pre-charge unit comprises:
a first transistor, wherein a gate of the first transistor is configured to receive a scan signal outputted by a previous four stage shift register, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal; and
a second transistor, wherein a gate of the second transistor is configured to receive a scan signal outputted by a next four stage shift register, a first source/drain of the second transistor is configured to receive a backward input signal, and a second source/drain of the second transistor is coupled to the second source/drain of the first transistor;

a pull-up unit coupled to the pre-charge unit, the pull-up unit configured to receive the pre-charge signal and a clock signal and to output a scan signal via a second node based on the pre-charge signal and the clock signal;
a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and to control whether to pull down the scan signal to a first reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and
a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and to control whether to keep the scan signal at the first reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
wherein a duty cycle of the clock signal is less than 50 percent.

2. The shift register of claim 1 , wherein a high level duration of the clock signal is half of a clock period of the clock signal subtracted by a data writing period.

3. The shift register of claim 1 , wherein the pull-up unit comprises:
a third transistor, wherein a gate of the third transistor is configured to receive the pre-charge signal, a first source/drain of the third transistor is configured to receive the clock signal, and a second source/drain of the third transistor is configured to output the scan signal; and
a capacitor, wherein a first terminal of the capacitor is coupled to the gate of the third transistor, and a second terminal of the capacitor is coupled to the second source/drain of the third transistor.

4. The shift register of claim 1 , wherein the first pull-down unit comprises:
a fourth transistor, wherein a gate and a first source/drain of the fourth transistor are configured to input the first pull-down control signal;
a fifth transistor, wherein a gate of the fifth transistor is configured to input the second pull-down control signal, a first source/drain of the fifth transistor is configured to input the first reference voltage level, and a second source/drain of the fifth transistor is coupled to the second source/drain of the fourth transistor;
a sixth transistor, wherein a gate of the sixth transistor is coupled to the first node, a first source/drain of the sixth transistor is configured to input the first reference voltage level, and a second source/drain of the sixth transistor is coupled to the second source/drain of the fourth transistor;
a seventh transistor, wherein a gate of the seventh transistor is coupled to the second source/drain of the sixth transistor, a first source/drain of the seventh transistor is configured to input the first reference voltage level, and a second source/drain of the seventh transistor is coupled to the first node; and
an eighth transistor, wherein a gate of the eighth transistor is coupled to the second source/drain of the sixth transistor, a first source/drain of the eighth transistor is configured to input a second reference voltage level, and a second source/drain of the eighth transistor is coupled to the second node.

5. The shift register of claim 4 , wherein the second reference voltage level is substantially lower than the first reference voltage level.

6. The shift register of claim 5 , wherein a difference between the second reference voltage level and the first reference voltage level is substantially 3 volts.

7. The shift register of claim 1 , wherein the second pull-down unit comprises:
a ninth transistor, wherein a gate and a first source/drain of the ninth transistor are configured to input the second pull-down control signal;
a tenth transistor, wherein a gate of the tenth transistor is configured to input the first pull-down control signal, a first source/drain of the tenth transistor is configured to input the first reference voltage level, and a second source/drain of the tenth transistor is coupled to the second source/drain of the ninth transistor;
an eleventh transistor, wherein a gate of the eleventh transistor is coupled to the first node, a first source/drain of the eleventh transistor is configured to input the first reference voltage level, and a second source/drain of the eleventh transistor is coupled to the second source/drain of the ninth transistor;
a twelfth transistor, wherein a gate of the twelfth transistor is coupled to the second source/drain of the eleventh transistor, a first source/drain of the twelfth transistor is configured to input the first reference voltage level, and a second source/drain of the twelfth transistor is coupled to the first node; and
a thirteenth transistor, wherein a gate of the thirteenth transistor is coupled to the second source/drain of the eleventh transistor, a first source/drain of the thirteenth transistor is configured to input a second reference voltage level, and a second source/drain of the thirteenth transistor is coupled to the second node.

8. The shift register of claim 7 , wherein the second reference voltage level is substantially lower than the first reference voltage level.

9. The shift register of claim 8 , wherein a difference between the second reference voltage level and the first reference voltage level is substantially 3 volts.

10. A display apparatus, comprising:
a display panel; and
a gate driver configured to drive the display apparatus and having 1 st -N th stage shift registers, wherein the i th stage shift register of the 1 st -N th stage shift registers comprises:
a pre-charge unit configured to receive a first input signal and a second input signal and output a pre-charge signal via a first node based on the first input signal and the second input signal, wherein the pre-charge unit of the i th stage shift register comprises:
a first transistor, wherein a gate of the first transistor is configured to receive a first input signal, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal; and
a second transistor, wherein a gate of the second transistor is configured to receive a second input signal, a first source/drain of the second transistor is configured to receive a backward input signal, and a second source/drain of the second transistor is coupled to the second source/drain of the first transistor, wherein:
when i is from 1 to 4, the first input signal is a starting signal, and the second input signal is an (i+4) th stage scan

Assignees

• Hannstar Display Nanjing Corp
• Hannstar Display Corp

Inventors

• Chan Chien-Ting

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title