Shift register unit, gate electrode drive circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-9524686-B2
Application number	US-201414436932-A
Country	US
Kind code	B2
Filing date	Jul 30, 2014
Priority date	Mar 27, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

The present disclosure provides a shift register unit, a gate electrode drive circuit and a display apparatus, which relates to a technical field of display. The shift register unit includes an input reset module, a pull up module, a control module and a pull down module. By inputting a high level into the second signal input end of the input reset module in the touch scan to maintain the level at the pull up control node, the electrical leak effects at the pull up control node may be avoided efficiently. In this way, the defects of insufficient charging rate of the row pixels may be avoided and the dark lines or bad bright lines may be suppressed.

First claim

What is claimed is:

1. A shift register unit, comprising:
an input reset module which has a first signal input end, a second signal input end, a first voltage connecting end, a second voltage connecting end and a first pull up control node connecting end, and is configured to control a level at the pull up control node depending on a signal inputted from the first signal input end and the second signal input end;
a pull up module which has a first clock signal input end, a second pull up control node connecting end and a pull up module signal output end and is configured to selectively pull up the signal outputted from the pull up module signal output end to a high level depending on the level at the pull up control node and the clock signal inputted from the first clock signal input end;
a control module which has a second clock signal input end, a first connecting end for a third voltage, a third pull up control node connecting end and a first pull down control node connecting end and is configured to control a level at the pull down control node depending on the clock signal inputted from the second clock signal input end and the level at the pull up control node; and
a pull down module which has a fourth pull up control node connecting end, a second pull down control node connecting end, a second connecting end for the third voltage, a fourth voltage connecting end and a pull down module signal output end and is configured to selectively pull down the signal outputted from the pull down module signal output end to a low level,
wherein the first voltage connecting end is connected to a first voltage input end of the shift register unit, the second voltage connecting end is connected to a second voltage input end of the shift register unit, the first connecting end for the third voltage and the second connecting end for the third voltage are both connected to the third voltage input end of the shift register unit, the fourth voltage connecting end is connected to a fourth voltage input end of the shift register unit, the pull up module signal output end and the pull down module signal output end are connected to form a signal output end of the shift register unit, the pull up control node being a connecting point connected with the first pull up control node connecting end, the second pull up control node connecting end, the third pull up control node connecting end and the fourth pull up control node connecting end, the pull down control node being a connecting point connected with the first pull down control node connecting end and the second pull down control node connecting end, wherein the high level is inputted into the second signal input end in a touch scan to maintain the level at the pull up control node.

2. The shift register unit according to claim 1 , wherein the input reset module comprises:
a first transistor which has a first electrode connected to the first pull up control node connecting end, a gate electrode connected to the first signal input end and a second electrode connected to the first voltage connecting end, the first electrode of the first transistor being one of a source electrode and a drain electrode of the first transistor, the second electrode of the first transistor being the other of the source electrode and the drain electrode of the first transistor; and
a second transistor which has a first electrode connected to the second voltage connecting end, a gate electrode connected to the second signal input end and a second electrode connected to the first pull up control node connecting end, the first electrode of the second transistor being one of a source electrode and a drain electrode of the second transistor, the second electrode of the second transistor being the other of the source electrode and the drain electrode of the second transistor.

3. The shift register unit according to claim 2 , wherein the signal inputted from the first voltage connecting end is a signal inputted from the first signal input end.

4. The shift register unit according to claim 1 , wherein the pull up module comprises:
a third transistor which has a first electrode connected to the pull up module signal output end, a gate electrode connected to the second pull up control node connecting end and a second electrode connected to the first clock signal input end, the first electrode of the third transistor being one of a source electrode and a drain electrode of the third transistor, the second electrode of the third transistor being the other of the source electrode and the drain electrode of the third transistor; and
a capacitance connected between the gate electrode of the third transistor and the first electrode of the third transistor.

5. The shift register unit according to claim 1 , wherein the control module comprises:
a fourth transistor which has a gate electrode and a second electrode both connected to the second clock signal input end;
a fifth transistor which has a gate electrode connected to a first electrode of the fourth transistor and a second electrode connected to the second clock signal input end;
a sixth transistor which has a first electrode connected to the first connecting end for the third voltage, a gate electrode connected to the third pull up control node connecting end and a second electrode connected to the first electrode of the fourth transistor;
a seventh transistor which has a first electrode connected to the first connecting end for the third voltage, a gate electrode connected to the third pull up control node connecting end and a second electrode connected to the first pull down control node connecting end,
wherein the first electrode of any one transistor of the fourth to seventh transistors being one of a source electrode and a drain electrode of the one transistor, the second electrode of any one transistor of the fourth to seventh transistors being the other of the source electrode and the drain electrode of the one transistor.

6. The shift register unit according to claim 3 , wherein the pull down module comprises:
an eighth transistor which has a first electrode connected to the fourth voltage connecting end, a gate electrode connected to the second pull down control node connecting end and a second electrode connected to the fourth pull up control node connecting end, wherein an input voltage at the fourth voltage connecting end is the same as that at the second voltage connecting end;
a ninth transistor which has a first electrode connected to the second connecting end for the third voltage, a gate electrode connected to the second pull down control node connecting end and a second electrode connected to the pull down module signal output end,
wherein the first electrode of any one transistor of the eighth to ninth transistors being one of a source electrode and a drain electrode of the one transistor, the second electrode of any one transistor of the eighth to ninth transistors being the other of the source electrode and the drain electrode of the one transistor.

7. The shift register unit according to claim 1 , wherein the pull down module comprises:
an eighth transistor which has a first electrode connected to the fourth voltage connecting end, a gate electrode connected to the second pull down control node connecting end and a second electrode connected to the fourth pull up control node connecting end; and
a ninth transistor which has a first electrode connected to the second connecting end for the third voltage, a gate electrode connected to the second pull down control node connecting end and a second electrode connected to the pull down module signal output end.

8. A gate electrode drive circuit, comprising a plurality of shift register units cascaded to each other, wherein touch scan

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Yuanbo
• Zhao Jiayang
• Han Seung Woo
• Yao Xing
• Jin Haifeng

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G3/36

  using liquid crystals · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title