Computation-in-memory in three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-11114434-B2
Application number	US-201916542274-A
Country	US
Kind code	B2
Filing date	Aug 15, 2019
Priority date	Jun 28, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a first semiconductor structure including a peripheral circuit, a data processing circuit, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. In addition, the 3D memory device includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit, a data processing circuit, and a first bonding layer comprising a plurality of first bonding contacts;
a second semiconductor structure comprising an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts; and
a bonding interface between the first bonding layer and the second bonding layer, wherein
the first bonding contacts are in contact with the second bonding contacts at the bonding interface,
the first semiconductor structure is above the second semiconductor structure, and
the first semiconductor structure further comprises a semiconductor layer above the first bonding layer, and a pad-out interconnect layer above the semiconductor layer.

2. The 3D memory device of claim 1 , wherein the semiconductor layer comprises at least one of polysilicon or single-crystal silicon.

3. The 3D memory device of claim 1 , wherein the second semiconductor structure comprises:
a substrate;
a memory stack above the substrate;
the array of 3D NAND memory strings extending vertically through the memory stack; and
the second bonding layer above the memory stack and the array of 3D NAND memory strings.

4. The 3D memory device of claim 3 , wherein in the first semiconductor structure:
the first bonding layer is above the second bonding layer;
the peripheral circuit is above the first bonding layer;
the data processing circuit is above the first bonding layer and non-overlapping with the peripheral circuit; and
the semiconductor layer is above and in contact with the peripheral circuit and the data processing circuit.

5. The 3D memory device of claim 1 , wherein the data processing circuit comprises a field-programmable gate array (FPGA).

6. The 3D memory device of claim 1 , wherein the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the data processing circuit, and the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of 3D NAND memory strings.

7. The 3D memory device of claim 6 , wherein the data processing circuit is electrically connected to the array of 3D NAND memory strings through the first and second interconnect layers and the first and second bonding contacts.

8. The 3D memory device of claim 1 , wherein the pad-out interconnect layer comprises one or more interconnects in an interlayer dielectric (ILD) layer.

9. The 3D memory device of claim 8 , wherein the interconnects comprise contact pads.

10. The 3D memory device of claim 1 , wherein the pad-out interconnect layer is configured to transfer electrical signals between the 3D memory device and one or more outside circuits outside the 3D memory device.

11. The 3D memory device of claim 10 , wherein the peripheral circuit and the data processing circuit are electrically connected to the one or more outside circuits through the pad-out interconnect layer.

12. The 3D memory device of claim 6 , wherein the first semiconductor structure further comprises one or more contacts extending through the semiconductor layer to electrically connect the pad-out interconnect layer with the first interconnect layer.

13. The 3D memory device of claim 1 , wherein the peripheral circuit and the data processing circuit are stacked over one another on different planes.

14. The 3D memory device of claim 1 , wherein the array of 3D NAND memory strings comprise a plurality of floating gate NAND memory strings, and the semiconductor layer comprises a source plate of the plurality of floating gate NAND memory strings.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Yang Shengwei
• Xia Zhongyi
• Han Kun

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W72/941

  Dispositions of bond pads · CPC title