Semiconductor device with a layered protection mechanism and associated systems, devices, and methods

Patent metadata

Field	Value
Publication number	US-11114415-B2
Application number	US-202016823028-A
Country	US
Kind code	B2
Filing date	Mar 18, 2020
Priority date	Jan 24, 2018
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

First claim

We claim:

1. A semiconductor device, comprising:
a first die;
a second die attached over the first die;
a first metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and
a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level;
wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

2. The semiconductor device of claim 1 , wherein the first metal enclosure and the second metal enclosure do not directly contact each other.

3. The semiconductor device of claim 2 , wherein the first metal enclosure and the second metal enclosure are separated by an enclosure separation distance, wherein the enclosure separation distance correlates to the enclosure capacitance.

4. The semiconductor device of claim 3 , wherein the enclosure separation distance is uniform between the first metal enclosure and the second metal enclosure.

5. The semiconductor device of claim 2 , wherein the first metal enclosure and the second metal enclosure form an enclosure separation space between the first die and the second die, wherein the enclosure separation space continuously encircles a set of one or more internal interconnects, wherein the enclosure separation space is vacuum, filled with a gas, or filled with a dielectric material.

6. The semiconductor device of claim 1 , wherein the first die and the second die are singulated semiconductor dies that comprise a die stack.

7. The semiconductor device of claim 6 , wherein:
the second metal enclosure is an outer enclosure that encircles an overall enclosed space;
the first metal enclosure is a first inner enclosure that encircles a first inner space; and further comprising:
a second inner enclosure directly contacting and vertically extending between the first die and the second die, wherein the second inner enclosure peripherally encircles a second inner space that is within the overall enclosed space and mutually exclusive from the first inner space.

8. The semiconductor device of claim 1 , further comprising:
a third die attached over the second die;
an upper-level inner enclosure directly contacting and vertically extending between the second die and the third die and configured to electrically connect to the first voltage level; and
an upper-level outer enclosure directly contacting and vertically extending between the second die and the third die, wherein the upper-level outer enclosure peripherally encircles the upper-level inner enclosure and is configured to electrically connect to the second voltage level.

9. The semiconductor device of claim 1 , wherein:
one or more points, surfaces, or portions on each of the upper-level inner enclosure and the lower-level inner enclosure are coincident along a first vertical line; and
one or more points, surfaces, or portions on each of the upper-level outer enclosure and the lower-level outer enclosure are coincident along a second vertical line.

10. The semiconductor device of claim 1 , wherein;
the second metal enclosure is an outer-most enclosure along a horizontal direction; and
the second metal enclosure is electrically coupled to electrical ground.

11. A semiconductor device including a die stack having at least two dies, comprising:
a plurality of interconnects electrically coupling two or more adjacent dies of the die stack; and
a first metal sealing member and a second metal sealing member disposed between a pair of adjacent dies, wherein
the first metal sealing member is configured to connect to a first voltage level,
the second metal sealing member is configured to connect to a second voltage level, and
the first metal sealing member encloses one or more interconnects and is nested within the second metal sealing member for providing an enclosure capacitance surrounding the one or more interconnects.

Assignees

• Micron Technology Inc

Inventors

• Zhou Wei
• Street Bret K

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/012

  of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills · CPC title

• H10W70/421

  Shapes or dispositions · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title