Systems and methods for faster read after write forwarding using a virtual address

Patent metadata

Field	Value
Publication number	US-9767020-B2
Application number	US-201514819255-A
Country	US
Kind code	B2
Filing date	Aug 5, 2015
Priority date	Aug 30, 2013
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible.

First claim

We claim:

1. A method for read-after-write forwarding using a virtual address, said method comprising:
determining if a load and a store are to a same page;
if said load and said store are to said same page, completing said load with data acquired via virtual-address-based forwarding while said load and said store are delayed for acquisition of their respective physical addresses and while the physical address of said load is cross-checked against the physical address of said store; and
retiring said load if said cross checking indicates that said load and said store have different physical addresses.

2. The method of claim 1 , further comprising flushing an instruction pipeline if said cross checking indicates that said load and said store have the same physical address, wherein said load, and every instruction subsequent to it, is flushed.

3. The method of claim 1 , wherein said same page is 4 k in size.

4. The method of claim 1 , further comprising signaling a hazard during said completing.

5. A cache system, comprising:
data storage components; and
a cache controller, wherein said cache controller includes a system that comprises:
a determining component for determining if a load and a store are to a same page;
a hazard signaling/load completing component, wherein responsive to a determination that said load and said store are to said same page, said load completing component is operable to complete said load with data acquired via virtual-address-based forwarding while said load and said store are delayed for acquisition of their respective physical addresses and while the physical address of said load is cross-checked against the physical address of said store,
wherein said load is retired if said cross checking indicates that said load and said store have different physical addresses.

6. The cache system of claim 5 , wherein if said cross checking indicates that said load and said store have the same physical address an instruction pipeline is flushed such that said load and every instruction subsequent to it is flushed.

7. The cache system of claim 5 , wherein said same page is 4 k in size.

8. The cache system of claim 5 , wherein said hazard signaling/load completing component is further operable to signal a hazard while said load is completing.

9. A computer system, comprising:
a memory;
a processor;
a cache system; and
a cache controller, wherein said cache controller comprises:
a determining component for determining if a load and a store are to a same page;
a hazard signaling/load completing component, wherein responsive to a determination that said load and said store are to said same page, said load completing component is operable to complete said load with data acquired via virtual address based forwarding while said load and said store are delayed for acquisition of their respective physical addresses and while the physical address of said load is cross-checked against the physical address of said store,
wherein said load is retired if said cross checking indicates that said load and said store have different physical addresses.

10. The computer system of claim 9 , wherein if said cross checking indicates that said load and said store have the same physical address an instruction pipeline is flushed such that said load and every instruction subsequent to it is flushed.

11. The computer system of claim 9 , wherein said same page is 4 k in size.

12. The computer system of claim 9 , wherein said hazard signaling/load completing component is further operable to signal a hazard while said load is completing.

Assignees

• Intel Corp

Inventors

• Avudaiyappan Karthikeyan
• Chan Paul

Classifications

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F2212/654

  Look-ahead translation · CPC title

• G06F12/08 Primary

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title