Systems and methods for faster read after write forwarding using a virtual address

Patent metadata

Field	Value
Publication number	US-10402322-B2
Application number	US-201715686721-A
Country	US
Kind code	B2
Filing date	Aug 25, 2017
Priority date	Aug 30, 2013
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible.

First claim

We claim:

1. A method for performing read after write forwarding in a processor, the method comprising:
determining that a virtual address associated with a load instruction has been remapped from a first physical address to a second physical address; and
delaying the load instruction from executing until all store instructions in a store queue that are older than the remapping of the virtual address from the first physical address to the second physical address have retired.

2. The method of claim 1 , further comprising:
determining that all store instructions in the store queue that are older than the remapping of the virtual address from the first physical address to the second physical address have retired; and
executing the load instruction in response to determining all store instructions in the store queue that are older than the remapping of the virtual address from the first physical address to the second physical address have retired.

3. The method of claim 1 , further comprising:
determining that the virtual address of the load instruction is the same as a store instruction in the store queue,
wherein delaying the execution of the load instruction is performed in response to determining that the virtual address of the load instruction is the same as the store instruction in the store queue.

4. The method of claim 3 , wherein the second physical address is different from a physical address of the store instruction.

5. The method of claim 1 , wherein determining that the virtual address associated with the load instruction has been remapped from the first physical address to the second physical address is based on an indicator provided by an operating system.

6. The method of claim 1 , wherein upon a store instruction being retired, the store instruction is globally visible in the processor.

7. The method of claim 1 , wherein the method is performed by a cache controller of a cache of the processor.

8. A processor for performing read after write forwarding, the processor comprising:
a remapping determiner to determine that a virtual address associated with a load instruction has been remapped from a first physical address to a second physical address; and
a load enabler to delay the load instruction from executing until all store instructions in a store queue that are older than the remapping of the virtual address from the first physical address to the second physical address have retired.

9. The processor of claim 8 , further comprising:
a store retirement determiner to determine that all store instructions in the store queue that are older than the remapping of the virtual address from the first physical address to the second physical address have retired such that the load instruction is executed only after determining all store instructions in the store queue that are older than the remapping of the virtual address from the first physical address to the second physical address have retired.

10. The processor of claim 8 , wherein the virtual address of the load instruction is the same as a store instruction in the store queue, and
wherein the load enabler delays the execution of the load instruction in response to determining that the virtual address of the load instruction is the same as the store instruction in the store queue.

11. The processor of claim 10 , wherein the second physical address is different from a physical address of the store instruction.

12. The processor of claim 8 , wherein the remapping determiner determines that the virtual address associated with the load instruction has been remapped from the first physical address to the second physical address is based on an indicator provided by an operating system.

13. The processor of claim 8 , wherein upon a store instruction being retired, the store instruction is globally visible in the processor.

14. A non-transitory machine-readable medium storing instruction that when executed by a processor, cause the processor to:
determine that a virtual address associated with a load instruction has been remapped from a first physical address to a second physical address; and
delay the load instruction from executing until all store instructions in a store queue that are older than the remapping of the virtual address from the first physical address to the second physical address have retired.

15. The non-transitory machine-readable medium of claim 14 , wherein the instructions when executed by the processor further cause the processor to:
determine that all store instructions in the store queue that are older than the remapping of the virtual address from the first physical address to the second physical address have retired; and
execute the load instruction in response to determining all store instructions in the store queue that are older than the remapping of the virtual address from the first physical address to the second physical address have retired.

16. The non-transitory machine-readable medium of claim 14 , wherein the instructions when executed by the processor further cause the processor to:
determine that the virtual address of the load instruction is the same as a store instruction in the store queue,
wherein delaying the execution of the load instruction is performed in response to determining that the virtual address of the load instruction is the same as the store instruction in the store queue.

17. The non-transitory machine-readable medium of claim 16 , wherein the second physical address is different from a physical address of the store instruction.

18. The non-transitory machine-readable medium of claim 14 , wherein determining that the virtual address associated with the load instruction has been remapped from the first physical address to the second physical address is based on an indicator provided by an operating system.

19. The non-transitory machine-readable medium of claim 14 , wherein upon a store instruction.

Assignees

• Intel Corp

Inventors

• Avudaiyappan Karthikeyan
• Chan Paul

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F12/10

  Address translation · CPC title