Buried power rail for transistor devices

Patent metadata

Field	Value
Publication number	US-11101217-B2
Application number	US-201916455148-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Jun 27, 2019
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

A method of forming a buried power rail for transistor devices is provided. The method includes forming an adjacent pair of transistor devices on a substrate, wherein the adjacent pair of transistor devices is separated by a gap distance, GD, filled by a fill layer. The method further includes forming a dielectric plate between the adjacent pair of transistor devices by removing a portion of the fill layer, and forming a protective liner on each of the adjacent pair of transistor devices. The method further includes forming a sidewall spacer on each of the protective liners, and forming a buried power rail on the dielectric plate and between the sidewall spacers. The method further includes removing a portion of the sidewall spacers above the buried power rail to form spacer bars on the dielectric plate, and forming a power rail cap on the buried power rail and spacer bars.

First claim

What is claimed is:

1. A method of forming a buried power rail for transistor devices, comprising:
forming an adjacent pair of transistor devices on a substrate, wherein the adjacent pair of transistor devices is separated by a gap distance, G D , filled by a fill layer;
forming a dielectric plate between the adjacent pair of transistor devices by removing a portion of the fill layer to expose at least a portion of the sidewalls of the adjacent pair of transistor devices;
forming a sidewall spacer on each of the adjacent pair of transistor devices;
forming the buried power rail on the dielectric plate and between the sidewall spacers;
removing a portion of the sidewall spacers above the buried power rail to form spacer bars on the dielectric plate; and
forming a power rail cap on the buried power rail and spacer bars.

2. The method of claim 1 , further comprising, forming a dielectric plug layer on the power rail cap, wherein the power rail cap is over a top surface of each of the spacer bars, and etching back the dielectric plug layer to form a dielectric plug between the adjacent pair of transistor devices.

3. The method of claim 2 , further comprising, reducing the height of the dielectric plug to form a dielectric slab on the power rail cap.

4. The method of claim 3 , further comprising, forming an upper fill layer on the dielectric slab and between the adjacent pair of transistor devices.

5. The method of claim 4 , further comprising, forming a contact trench in the upper fill layer that exposes a portion of the power rail cap.

6. The method of claim 5 , further comprising, forming a buried contact on the exposed portion of the power rail cap.

7. The method of claim 6 , further comprising forming a conductive device contact on each of the adjacent pair of transistor devices.

8. The method of claim 6 , wherein a tip-to-tip distance, G C , between the conductive device contacts is in a range of about 20 nm to about 50 nm.

9. A method of forming a buried power rail for transistor devices, comprising:
forming an adjacent pair of transistor devices on a substrate, wherein the adjacent pair of transistor devices is separated by a gap distance, G D , filled by a fill layer;
forming a dielectric plate between the adjacent pair of transistor devices by removing a portion of the fill layer;
forming a sidewall spacer on each of the adjacent pair of transistor devices, wherein a portion of the dielectric plate is exposed between the sidewall spacers;
forming a buried power rail on the dielectric plate and between the sidewall spacers;
removing a portion of the sidewall spacers above the buried power rail to form spacer bars on the dielectric plate;
forming a metal power rail cap on the buried power rail and spacer bars;
forming a dielectric slab on the metal power rail cap; and
forming a source/drain on each of the adjacent pair of transistor devices.

10. The method of claim 9 , wherein the gap distance, G D , is in a range of about 30 nanometers (nm) to about 150 nm.

11. The method of claim 10 , further comprising forming a conductive device contact on each of the source/drains.

12. The method of claim 11 , wherein a tip-to-tip distance, G C , between the conductive device contacts is in a range of about 20 nm to about 50 nm.

13. A method of forming a buried power rail for transistor devices, comprising:
forming an adjacent pair of transistor devices on a substrate, wherein the adjacent pair of transistor devices is separated by a gap distance, G D , filled by a fill layer;
forming a dielectric plate between the adjacent pair of transistor devices by removing a portion of the fill layer;
forming a protective liner on each of the adjacent pair of transistor devices;
forming a sidewall spacer on each of the protective liners;
forming a buried power rail on the dielectric plate and between the sidewall spacers;
removing a portion of the sidewall spacers above the buried power rail to form spacer bars on the dielectric plate;
forming a power rail cap on the buried power rail and spacer bars;
forming a dielectric plug on the power rail cap between the protective liners;
removing a portion of the protective liners above the dielectric plug to form protective liner segments; and
reducing the height of the dielectric plug to form a dielectric slab on the power rail cap.

14. The method of claim 13 , wherein the dielectric plug is formed by depositing a dielectric plug layer on the power rail cap, and etching back the dielectric plug layer to form the dielectric plug.

15. The method of claim 13 , wherein the portion of the fill layer removed to form the dielectric plate also exposes at least a portion of the sidewalls of the adjacent pair of transistor devices.

16. The method of claim 13 , wherein a top surface of the dielectric plate is exposed between the sidewall spacers before forming the buried power rail.

17. The method of claim 16 , further comprising, forming an upper fill layer on the dielectric slab and protective liner segments.

18. The method of claim 17 , wherein the protective liners are a dielectric material selected from the group consisting of silicon carbide (SiC), silicon oxycarbide (SiOC), and a combination thereof.

19. The method of claim 17 , wherein the power rail cap is over a top surface of each of the spacer bars, and wherein the power rail cap is made of a metal.

Assignees

• IBM

Inventors

• Xie Ruilong
• Reznicek Alexander
• Wang Junli
• Cheng Kangguo

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10P50/283

  by chemical means · CPC title