Method for plating printed circuit board and printed circuit board using the same

Patent metadata

Field	Value
Publication number	US-11096291-B2
Application number	US-201916710697-A
Country	US
Kind code	B2
Filing date	Dec 11, 2019
Priority date	Jun 25, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A method for plating a printed circuit board, includes placing a substrate, including a through hole, in contact with a plating solution and disposing the substrate to face an electrode; and applying a pulsed current to each surface of the substrate, including applying pulsed currents of opposite polarity to both surfaces of the substrate at least once and applying pulsed forward currents to both surfaces of the substrate at least once, to plate from a middle to an end of the through hole.

First claim

What is claimed is:

1. A printed circuit board comprising:
a substrate in which a through hole is formed; and
a via filling the through hole and extending to both surfaces of the substrate,
wherein the via comprises
a first plating layer formed in the through hole, extending to both surfaces of the substrate, and having a recessed groove formed in the surface of the substrate at both ends of the substrate, and
a second plating layer filling the groove, formed on the first plating layer, and extending onto the substrate,
wherein the first plating layer has a greater grain size at a region disposed at a lower part of the groove than a region disposed at a center part of the through hole.

2. The printed circuit board of claim 1 , wherein the first plating layer comprises:
a fine grain region extending to an inner wall at the center of the through hole; and
a coarse grain region formed at a bottom part of the groove and surrounded by the fine grain region,
wherein metal particles of the coarse grain region are larger than metal particles of the fine grain region.

3. The printed circuit board of claim 2 , wherein the fine grain region extends along the inner wall of the through hole to a surface of the substrate.

4. The printed circuit board of claim 3 , wherein the fine grain region comprises:
a first fine grain region extending toward the inner wall at the center of the through hole; and
a second fine grain region disposed between the first fine grain region and the coarse grain region and extending along the inner wall of the through hole toward the surface of the substrate,
wherein metal particles of the second fine grain region are smaller than metal particles of the first fine grain region.

5. The printed circuit board of claim 1 , wherein a depth of the groove in the first plating layer is 150 μm or less and a circuit pattern connected to the via is formed on the substrate to have a thickness of 30 μm or less.

6. The printed circuit board of claim 1 , further comprising a seed layer located on an inner wall of the through hole and on a surface of the substrate, wherein the first plating layer is an electroplating layer formed on the seed layer.

7. The printed circuit board of claim 1 , further comprising a copper foil layer located on the substrate and a seed layer located on an inner wall of the through hole and on the copper foil layer, wherein the first plating layer is an electroplating layer formed on the seed layer.

8. The printed circuit board of claim 1 , wherein the substrate is an insulating material without a circuit layer located on the substrate.

9. The printed circuit board of claim 1 , wherein the substrate comprises a buildup layer having a plurality of circuit layers formed on the buildup layer.

10. The printed circuit board of claim 1 , wherein a thickness of the first plating layer is larger than a thickness of the second plating layer on the surface of the substrate.

11. A printed circuit board comprising:
a substrate in which a through hole is formed, wherein a via fills the through hole and extends to both surfaces of the substrate,
wherein the via comprises
a first plating layer formed in the through hole, and
a second plating layer formed on the first plating layer,
wherein the first plating layer has a fine grain region and a coarse grain region and wherein metal particles of the coarse grain region are larger than metal particles of the fine grain region.

12. The printed circuit board of claim 11 , wherein the first plating layer extends onto both surfaces of the substrate, and has a recessed groove formed in the surface of the substrate at both ends of the substrate.

13. The printed circuit board of claim 11 , wherein the second plating layer fills the groove and extends onto the substrate.

14. The printed circuit board of claim 11 , wherein the fine grain region extends along the inner wall of the through hole to a surface of the substrate.

15. The printed circuit board of claim 11 , wherein the fine grain region comprises:
a first fine grain region extending toward the inner wall at the center of the through hole; and
a second fine grain region disposed between the first fine grain region and the coarse grain region and extending along the inner wall of the through hole toward the surface of the substrate,
wherein metal particles of the second fine grain region are smaller than metal particles of the first fine grain region.

Assignees

• Samsung Electro Mech

Inventors

• Choi Jong Chan
• Jeong Young Kwon
• Kim Min Soo
• Mun Seong Jae

Classifications

• C25D21/12

  Process control or regulation (controlling or regulating in general G05) · CPC title

• C25D5/02

  Electroplating of selected surface areas · CPC title

• C25D7/123

  Semiconductors first coated with a seed layer or a conductive layer · CPC title

• C25D5/18

  Electroplating using modulated, pulsed or reversing current · CPC title

• C25D3/38

  of copper · CPC title