Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit

Patent metadata

Field	Value
Publication number	US-11094820-B2
Application number	US-202016846461-A
Country	US
Kind code	B2
Filing date	Apr 13, 2020
Priority date	Mar 21, 2017
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.

First claim

What is claimed is:

1. A symmetric element of a resistive processing unit (RPU), the element comprising:
a substrate with a channel region connecting two doped regions;
a source above one of the two doped regions;
a drain above an other of the two doped regions, wherein the source and the drain are entirely above the channel region that connects the two doped regions;
a gate above the channel region;
a bar ferroelectric above the channel region and below the gate; and
a first electrode between the source and the gate and a second electrode between the drain and the gate, wherein the first electrode and the second electrode are directly on and entirely above the bar ferroelectric.

2. The element according to claim 1 , wherein the bar ferroelectric separates the source and the one of the two doped regions from the drain and the other of the two doped regions because the source and the one of the two doped regions are formed on an opposite side of the bar ferroelectric from the drain and the other of the two doped regions.

3. The element according to claim 1 , further comprising an insulator layer above the channel region.

4. The element according to claim 3 , wherein the insulator layer separates the channel region and the bar ferroelectric.

5. The element according to claim 3 , wherein the insulator layer separates the channel region from the first electrode and the second electrode above the bar ferroelectric.

6. The element according to claim 3 , further comprising a quantum metal above the insulator layer.

7. The element according to claim 6 , wherein the quantum metal separates the bar ferroelectric from the insulator layer.

8. The element according to claim 6 , wherein the quantum metal is doped Strontium Titanate.

9. The element according to claim 3 , wherein the insulator layer is an oxide, a nitride, or a high-k dielectric.

10. The element according to claim 1 , wherein the bar ferroelectric includes a first portion and a second portion separated by a domain wall.

11. The element according to claim 10 , wherein the first portion and the second portion have opposite polarities.

12. The element according to claim 1 , wherein a length of the bar ferroelectric is between 0.1 and 1 micrometers.

13. The element according to claim 1 , wherein the two doped regions are n++doped.

14. The element according to claim 1 , wherein the substrate includes a bulk semiconductor.

15. The element according to claim 1 , wherein the substrate includes an organic semiconductor or a layered semiconductor.

Assignees

• IBM

Inventors

• Han Jin-Ping
• Muralidhar Ramachandran
• Newns Dennis M
• Solomon Paul M

Classifications

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title

• H10D30/701 Primary

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H01L29/40111

  Electricity · mapped topic

• H01L29/78391 Primary

  Electricity · mapped topic