Integrated structures, capacitors and methods of forming capacitors

Patent metadata

Field	Value
Publication number	US-11087991-B2
Application number	US-201916514928-A
Country	US
Kind code	B2
Filing date	Jul 17, 2019
Priority date	Mar 6, 2017
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

First claim

We claim:

1. An integrated structure, comprising:
a semiconductor base;
an insulative frame over the semiconductor base; the insulative frame comprising vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets; the first and second insulative materials being different from one another; and
conductive plates between the vertically-spaced sheets, the conductive plates being directly against the insulative pillars.

2. The integrated structure of claim 1 wherein one of the first and second insulative materials comprises silicon dioxide and the other comprises silicon nitride.

3. The integrated structure of claim 1 wherein the conductive plates comprise metal.

4. The integrated structure of claim 1 wherein the conductive plates comprise one or more of tungsten, titanium, tungsten nitride and titanium nitride.

5. The integrated structure of claim 1 wherein the conductive plates are each subdivided amongst electrically isolated regions by the insulative pillars.

6. The integrated structure of claim 1 wherein the conductive plates are each a continuous sheet wrapping around the insulative pillars.

7. The integrated structure of claim 1 wherein the vertically-spaced sheets form first levels, and the conductive plates are along second levels which alternate with the first levels; and wherein the insulative pillars form walls which subdivide the conductive plates of individual second levels into panels.

8. The integrated structure of claim 7 wherein at least some of the panels of an individual second level are electrically coupled with one another.

9. The integrated structure of claim 7 wherein all of the panels of an individual second level are electrically coupled with one another.

10. The integrated structure of claim 7 wherein at least some of the panels of an individual second level are not electrically coupled with one another.

11. The integrated structure of claim 7 wherein none of the panels of an individual second level are electrically coupled with one another.

Assignees

• Micron Technology Inc

Inventors

• Freeman Eric
• Tessariol Paolo

Classifications

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10W44/601 Primary

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10D1/716

  having vertical extensions · CPC title