Integrated structures, capacitors and methods of forming capacitors

Patent metadata

Field	Value
Publication number	US-10366901-B2
Application number	US-201715451090-A
Country	US
Kind code	B2
Filing date	Mar 6, 2017
Priority date	Mar 6, 2017
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

First claim

We claim:

1. A capacitor comprising:
a stack of alternating first and second levels supported by a base; the first levels comprising only insulative material, and the second levels comprising insulative pillars extending through conductive material;
a plurality of slots extending through the stack; each of the slots comprised by the plurality of slots having a first end and an opposing second end with a central region between the first and second ends; the plurality of slots being arranged in multiple rows with the second ends of within a first row being spaced from the first ends of slots in a second row by a lateral distance; and
the insulative pillars within the second levels being within the lateral distance between rows of slots, the insulative pillars being of a different composition than the insulative material of the first levels.

2. The capacitor of claim 1 wherein the insulative pillars comprise silicon nitride; and wherein the insulative material of the first levels comprises silicon dioxide.

3. The capacitor of claim 1 wherein the slots extend along a first direction, and wherein the insulative pillars form walls extending along a second direction substantially orthogonal to the first direction; the walls subdividing the conductive material within each of the second levels into panels.

4. The capacitor of claim 3 wherein at least some of the panels of one of the second levels are electrically coupled with one another.

5. The capacitor of claim 3 wherein all of the panels of one of the second levels are electrically coupled with one another.

6. The capacitor of claim 3 wherein at least some of the panels of one of the second levels are not electrically coupled with one another.

7. The capacitor of claim 3 wherein none of the panels of one of the second levels are electrically coupled with one another.

8. The capacitor of claim 3 wherein the walls have substantially diamond shaped regions.

9. The capacitor of claim 1 wherein the conductive material of the second levels comprises metal.

10. The capacitor of claim 1 wherein the conductive material of the second levels comprises one or more of tungsten, titanium, tungsten nitride and titanium nitride.

11. The capacitor of claim 1 wherein the conductive material of each of the second levels is a continuous sheet wrapping around the insulative pillars.

12. The capacitor of claim 1 integrated into circuitry on a die together with a three-dimensional NAND memory array.

Assignees

• Micron Technology Inc

Inventors

• Freeman Eric
• Tessariol Paolo

Classifications

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10W44/601 Primary

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H01L28/86

  Electricity · mapped topic