Offset compensation for ferroelectric memory cell sensing

Patent metadata

Field	Value
Publication number	US-9858978-B2
Application number	US-201615377767-A
Country	US
Kind code	B2
Filing date	Dec 13, 2016
Priority date	Mar 11, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be connected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in conjunction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substantially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transistor. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

First claim

What is claimed is:

1. A method, comprising:
virtually grounding a digit line that is in electronic communication with a ferroelectric memory cell;
discharging an offset capacitor coupled to a gate of a first switching component based at least in part on virtually grounding the digit line; and
transferring a stored charge of the ferroelectric memory cell to a sense capacitor based at least in part on discharging the offset capacitor.

2. The method of claim 1 , further comprising:
coupling the ferroelectric memory cell to the sense capacitor via the first switching component based at least in part on discharging the offset capacitor.

3. The method of claim 1 , further comprising:
transferring a charge from the offset capacitor to the gate of the first switching component based at least in part on discharging the offset capacitor.

4. The method of claim 1 , wherein discharging the offset capacitor comprises:
applying a zero voltage to a second terminal of the offset capacitor; and
isolating a first terminal of the offset capacitor from the first switching component via a third switching component.

5. The method of claim 1 , further comprising:
activating a second switching component coupled to the first switching component or the sense capacitor, or both, wherein coupling the ferroelectric memory cell to the sense capacitor is based at least in part on activating the second switching component.

6. The method of claim 1 , further comprising:
activating a third switching component coupled to the digit line and to virtual ground, wherein virtually grounding the digit line is based at least in part on activating the third switching component.

7. The method of claim 1 , further comprising:
charging the offset capacitor before discharging the offset capacitor.

8. The method of claim 7 , wherein charging the offset capacitor comprises:
virtually grounding a first terminal of the offset capacitor through a second switching component, wherein the first terminal of the offset capacitor is in electronic communication with the gate of the first switching component and a drain of the first switching component; and
applying a voltage to a second terminal of the offset capacitor while the first terminal is virtually grounded.

9. The method of claim 1 , further comprising:
activating a sense component that is in electronic communication with the sense capacitor;
comparing a voltage of the sense capacitor to a reference voltage based at least in part on activating the sense component; and
identifying a logic state of the ferroelectric memory cell based at least in part on the comparison.

10. The method of claim 1 , further comprising:
activating a selection component of the ferroelectric memory cell, the selection component coupled to the digit line, wherein transferring the stored charge is based at least in part on activating the selection component.

11. The method of claim 1 , wherein the first switching component comprises a p-type field effect transistor (FET).

12. An electronic memory apparatus, comprising:
a ferroelectric memory cell coupled to a digit line, the ferroelectric memory cell configured to store a logic state;
a sense capacitor in electronic communication with the ferroelectric memory cell, the sense capacitor configured to store a charge indicative of the logic state;
a first switching component having a first terminal coupled to the digit line and a second terminal;
a second switching component coupled to the second terminal of the first switching component and the sense capacitor; and
a first offset capacitor coupled to a gate of the first switching component.

13. The electronic memory apparatus of claim 12 , further comprising:
a sense component in electronic communication with the sense capacitor.

14. The electronic memory apparatus of claim 12 , further comprising:
a third switching component coupled to the gate of the first switching component and the second terminal of the first switching component.

15. The electronic memory apparatus of claim 12 , further comprising:
a fourth switching component coupled to the offset capacitor, the gate of the first switching component, and a ground or a virtual ground.

16. The electronic memory apparatus of claim 12 , further comprising:
a voltage source coupled to the offset capacitor.

17. The electronic memory apparatus of claim 12 , further comprising:
a fifth switching component coupled to the digit line and a ground or a virtual ground.

18. An electronic memory apparatus, comprising:
a ferroelectric memory cell coupled to a digit line;
a sense component in electronic communication with the ferroelectric memory cell via the digit line;
a first switching component coupled to the digit line and the sense component;
an offset capacitor coupled to a gate of the first switching component;
a second switching component coupled to the digit line and to a ground or a virtual ground; and
a controller operable to:
activate the second switching component to virtually ground the digit line;
discharge the offset capacitor to transfer charge to the gate of the first switching component after the digit line is virtually grounded; and
activate the sense component based at least in part on discharging the offset capacitor.

19. The electronic memory apparatus of claim 18 , wherein the controller is operable to cause the apparatus to:
transfer a charge from a ferroelectric capacitor of the ferroelectric memory cell to a sense capacitor of the sense component.

20. The electronic memory apparatus of claim 18 , wherein the controller is operable to:
identify a logic state stored by the ferroelectric memory cell based at least in part on a comparison of a voltage of a sense capacitor to a voltage of a reference capacitor.

Assignees

• Micron Technology Inc

Inventors

• Vimercati Daniele

Classifications

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title