Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Patent metadata

Field	Value
Publication number	US-11086623-B2
Application number	US-201716487787-A
Country	US
Kind code	B2
Filing date	Jul 1, 2017
Priority date	Mar 20, 2017
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.

First claim

We claim:

1. A processor comprising:
decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand, wherein the matrices are multi-dimensional and the opcode is to indicate that execution circuitry is to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand; and
execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand.

2. The processor of claim 1 , wherein the execution circuitry comprises a grid of fused multiply accumulators.

3. The processor of claim 1 , wherein identified second source matrix operand is stored in memory.

4. The processor of claim 1 , wherein the multiplication is per row of the identified first source matrix operand and per column of the identified second source matrix operand.

5. The processor of claim 1 , wherein at least one of the operands is a plurality of registers configured to represent a matrix.

6. The processor of claim 1 , wherein the data elements are single precision floating point data elements.

7. The processor of claim 1 , wherein the data elements are half precision floating point data elements.

8. A method comprising:
decoding an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand, wherein the matrices are multi-dimensional and the opcode is to indicate the decoded instruction is to cause execution circuitry to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand; and
executing the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand.

9. The method of claim 8 , wherein the executing uses a grid of fused multiply accumulators.

10. The method of claim 8 , wherein identified second source matrix operand is stored in memory.

11. The method of claim 8 , wherein the multiplication is per row of the identified first source matrix operand and per column of the identified second source matrix operand.

12. The method of claim 8 , wherein at least one of the operands is a plurality of registers configured to represent a matrix.

13. The method of claim 8 , wherein the data elements are single precision floating point data elements.

14. The method of claim 8 , wherein the data elements are half precision floating point data elements.

15. A non-transitory machine-readable medium storing an instruction which causes a processor to perform a method, the method comprising:
decoding the instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand, wherein the matrices are multi-dimensional and the opcode is to indicate the decoded instruction is to cause execution circuitry to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand; and
executing the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand.

16. The non-transitory machine-readable medium of claim 15 , wherein the executing uses comprises a grid of fused multiply accumulators.

17. The non-transitory machine-readable medium of claim 15 , wherein identified second source matrix operand is stored in memory.

18. The non-transitory machine-readable medium of claim 15 , wherein the multiplication is per row of the identified first source matrix operand and per column of the identified second source matrix operand.

19. The non-transitory machine-readable medium of claim 15 , wherein at least one of the operands is a plurality of registers configured to represent a matrix.

20. A system comprising:
a processor; and
an accelerator coupled to the processor, the accelerator including:
decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand, wherein the matrices are multi-dimensional and the opcode is to indicate that execution circuitry is to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand; and
execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand.

Assignees

• Intel Corp

Inventors

• Valentine Robert
• Sperber Zeev
• Charney Mark J
• Toll Bret L
• Rappoport Rinat
• Shwartsman Stanislav
• Baum Dan
• Yanover Igor
• Ould-Ahmed-Vall Elmoustapha
• Adelman Menachem
• Corbal Jesus
• Gebil Yuri
• Rubanovich Simon

Classifications

• G06F2212/455

  Image or video data · CPC title

• G06F2212/454

  Vector or matrix data · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title