Systems, apparatuses, and methods for performing delta decoding on packed data elements

Patent metadata

Field	Value
Publication number	US-9557998-B2
Application number	US-201113997662-A
Country	US
Kind code	B2
Filing date	Dec 28, 2011
Priority date	Dec 28, 2011
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

Systems, apparatuses, and methods for performing delta decoding on packed data elements of a source and storing the results in packed data elements of a destination using a single packed delta decode instruction are described. A processor may include a decoder to decode an instruction, and execution unit to execute the decoded instruction to calculate for each packed data element position of a source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of a destination operand, and for each calculated value, store the value into a corresponding packed data element position of the destination operand.

First claim

What is claimed is:

1. A method comprising:
decoding a single instruction into a decoded single instruction with a decoder of a processor core; and
executing, in an execution unit of the processor core, the decoded single instruction that includes a source operand and a destination operand each having a same plurality of packed data elements to calculate for each packed data element position of the source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand, and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element position of the source operand.

2. The method of claim 1 , wherein the source and destination operands are vector registers.

3. The method of claim 2 , wherein the vector registers are 512-bits in size.

4. The method of claim 1 , wherein the packed data elements are 32-bits in size.

5. The method of claim 1 , wherein the values are instead calculated by adding all of the packed data elements of the source operand together to create a sum value, storing that sum value in a last packed data element position of the destination operand, and, for each packed data element position other than the last packed data element position, subtracting all data elements of the source operand that come from packed data element positions of greater significance from the sum value and storing that result in a corresponding packed data element position of the destination operand.

6. The method of claim 2 , wherein the vector registers are 128-bits in size.

7. The method of claim 2 , wherein the vector registers are 256-bits in size.

8. An apparatus comprising:
a hardware decoder to decode a single instruction that includes a source operand and a destination operand each having a same plurality of packed data elements into a decoded single instruction; and
an execution unit to execute the decoded single instruction to calculate for each packed data element position of the source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand, and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element position of the source operand.

9. The apparatus of claim 8 , further comprising:
a plurality of vector registers, wherein the source and destination operands are vector registers.

10. The apparatus of claim 9 , wherein the vector registers are 128-bits, 256-bits, or 512-bits in size.

11. The apparatus of claim 8 , wherein the packed data elements are 32-bits in size.

12. The apparatus of claim 8 , wherein the execution unit is to instead calculate values by adding all of the packed data elements of the source operand together to create a sum value, storing that sum value in a last packed data element position of the destination operand, and, for each packed data element position other than the last packed data element position, subtracting all data elements of the source operand that come from packed data element positions of greater significance from the sum value and store that result in a corresponding packed data element position of the destination operand.

13. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
decoding a single instruction into a decoded single instruction with a decoder of a processor core; and
executing, in an execution unit of the processor core, the decoded single instruction that includes a source operand and a destination operand each having a same plurality of packed data elements to calculate for each packed data element position of the source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand, and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element position of the source operand.

14. The non-transitory machine readable medium of claim 13 , wherein the source and destination operands are vector registers.

15. The non-transitory machine readable medium of claim 14 , wherein the vector registers are 256-bits in size.

16. The non-transitory machine readable medium of claim 14 , wherein the vector registers are 512-bits in size.

17. The non-transitory machine readable medium of claim 13 , wherein the packed data elements are 32-bits in size.

18. The non-transitory machine readable medium of claim 13 , wherein the values are instead calculated by adding all of the packed data elements of the source operand together to create a sum value, storing that sum value in a last packed data element position of the destination operand, and, for each packed data element position other than the last packed data element position, subtracting all data elements of the source operand that come from packed data element positions of greater significance from the sum value and storing that result in a corresponding packed data element position of the destination operand.

Assignees

• Ould-Ahmed-Vall Elmoustapha
• Willhalm Thomas
• Drysdale Tracy Garrett
• Intel Corp

Inventors

• Ould-Ahmed-Vall Elmoustapha
• Willhalm Thomas
• Drysdale Tracy Garrett

Classifications

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• H04N19/42

  characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title

• G06F9/30014

  with variable precision · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title