Method of manufacturing semiconductor devices using a capping layer in forming gate electrode and semiconductor devices

Patent metadata

Field	Value
Publication number	US-11081584-B2
Application number	US-201916532274-A
Country	US
Kind code	B2
Filing date	Aug 5, 2019
Priority date	Oct 30, 2018
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming an interfacial layer over a channel region;
forming a gate dielectric layer over the interfacial layer;
forming a first conductive layer over the gate dielectric layer;
forming a shield layer over the first conductive layer;
forming a capping layer over the shield layer;
performing a first annealing operation after the capping layer is formed;
removing the capping layer after the first annealing operation; and
forming a gate electrode layer over the gate dielectric layer after the capping layer is removed.

2. The method of claim 1 , wherein:
the first conductive layer is made of metal nitride, and
a thickness of the first conductive layer is in a range from 0.3 nm to 30 nm.

3. The method of claim 1 , wherein the shield layer is made of one selected from the group consisting of Si x N y (where 0.3≤x<0.75, 0.25≤y≤0.7, and x+y=1), Ti, Ti x C y (where 0.9≤x<0.99, 0.01≤y≤0.1, and x+y=1), Ti x Cl y (where 0.9≤x<0.99, 0.01≤y≤0.1, and x+y=1), titanium silicide, Ti x Si y (where 0.25≤x<0.99, 0.01≤y≤0.75, and x+y=1), Ti x N y (where 0.3≤x<0.99, 0.01≤y≤0.7, and x+y=1), and Si x Ti y N z (where 0.01≤x≤0.75, 0.01≤y≤0.99, 0.01≤y≤0.7, and x+y+z=1).

4. The method of claim 1 , wherein:
a thickness T 1 of the first conductive layer and a thickness T 2 of the shield layer satisfy 0.05≤T 2 /(T 1 +T 2 )≤0.85, and
the thickness T 2 of the shield layer is in a range from 0.5 nm to 30 nm.

5. The method of claim 1 , wherein the capping layer is made of crystalline, polycrystalline or amorphous silicon.

6. The method of claim 5 , wherein the capping layer includes fluorine.

7. The method of claim 1 , further comprising performing a second annealing operation before the capping layer is formed and after the shield layer is formed.

8. The method of claim 7 , wherein an annealing temperature of the first annealing operation is higher than an annealing temperature of the second annealing operation.

9. The method of claim 1 , wherein the shield layer is made of Si x Ti y N z , where 0≤x<1, 0≤y≤1, and 0≤z≤0.7.

10. The method of claim 9 , further comprising, after the capping layer is removed, removing the shield layer.

11. The method of claim 9 , further comprising performing a second annealing operation before the capping layer is formed and after the shield layer is formed.

12. The method of claim 10 , wherein after the shield layer is removed, an additional metal nitride layer made of a same material as the metal nitride layer is formed over the metal nitride layer.

13. A method of manufacturing a semiconductor device, comprising:
forming a gate dielectric layer over a channel region;
forming a first conductive layer over the gate dielectric layer;
forming a shield layer over the first conductive layer;
performing a first annealing operation after the shield layer is formed;
performing a fluorine soaking operation;
forming a capping layer over the shield layer;
performing a second annealing operation after the capping layer is formed;
removing the capping layer after the second annealing operation; and
forming a gate electrode layer over the gate dielectric layer after the capping layer is removed,
wherein the shield layer is removed after first annealing operation.

14. The method of claim 13 , wherein the first conductive layer is made of TiN.

15. The method of claim 13 wherein the shield layer is made of one selected from the group consisting of Si, Si x C y (where 0.9≤x<0.99, 0.01≤y≤0.1, and x+y=1), Si x Cl y (where 0.9≤x<0.99, 0.01≤y≤0.1, and x+y=1), Si x N y (where 0.3≤x<0.99, 0.01≤y≤0.7, and x+y=1), Ti, Ti x C y (where 0.9≤x<0.99, 0.01≤y≤0.1, and x+y=1), Ti x Cl y (where 0.9≤x<0.99, 0.01≤y≤0.1, and x+y=1), titanium silicide, Ti x Si y (where 0.01≤x<0.99, 0.01≤y≤0.99, and x+y=1), Ti x N y (where 0.3≤x<0.99, 0.01≤y≤0.7, and x+y=1), and Si x Ti y N z (where 0.01≤x<0.99, 0.01≤y≤0.99, 0.01≤y≤0.7, and x+y+z=1).

16. The method of claim 13 , wherein:
the annealing temperature of the first annealing operation is in a range from 600° C. to 800° C., and
the annealing temperature of the second annealing operation is in a range from 900° C. to 1300° C.

17. A method of manufacturing a semiconductor device, comprising:
forming a gate dielectric layer over a channel region;
forming a first conductive layer over the gate dielectric layer;
forming a shield layer over the first conductive layer;
performing a first annealing operation after the shield layer is formed;
forming a capping layer over the shield layer;
performing a second annealing operation after the capping layer is formed;
removing the capping layer after the second annealing operation; and
forming a gate electrode layer after the capping layer is removed,
wherein the shield layer is removed between the first annealing operation and the second annealing operation, or after the second annealing operation.

18. The method of claim 17 , wherein the first conductive layer is made of TiN.

19. The method of claim 17 , wherein the shield layer is made of Si x Ti y N z , where 0≤x<1, 0≤y≤1, 0≤z≤1, and x+y+z=1.

20. The method of claim 17 , wherein an annealing temperature of the first annealing operation is lower than an annealing temperature of the second annealing operation.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Savant Chandrashekhar Prakash
• Chong Kin Shun
• Yu Tien-Wei
• Tsai Chia-Ming
• Chen Ming-Te

Classifications

• H10P14/69394

  the material containing titanium, e.g. TiO2 · CPC title

• H10P14/6932

  the material containing titanium, e.g. TiSiOx · CPC title

• H10P14/6548

  by forming intermediate materials, e.g. capping layers or diffusion barriers · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title