Structure and formation method of semiconductor device structure with a dummy fin structure

US11081571B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11081571-B2
Application numberUS-202016928942-A
CountryUS
Kind codeB2
Filing dateJul 14, 2020
Priority dateJul 31, 2015
Publication dateAug 3, 2021
Grant dateAug 3, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure, and forming a mask layer covering the dummy fin structure. The method also includes removing a portion of the mask layer and a top portion of the dummy fin structure by a first etching operation to form an etched mask layer, wherein the dummy fin structure has a protruding portion protruding from a top surface of the etched mask layer after the first etching operation.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming a semiconductor device structure, comprising: forming a dummy fin structure; forming a mask layer covering the dummy fin structure; and removing a portion of the mask layer and a top portion of the dummy fin structure by a first etching operation to form an etched mask layer, wherein the dummy fin structure has a protruding portion protruding from a top surface of the etched mask layer after the first etching operation. 2. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising: irradiating the mask layer so that the mask layer is divided into an unirradiated portion and an irradiated portion before the first etching operation, wherein a first sidewall of the dummy fin structure is covered by the unirradiated portion, and a second sidewall of the dummy fin structure is covered by the irradiated portion. 3. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising: removing a middle portion of the dummy fin structure, such that the dummy fin structure has a concave top surface. 4. The method for forming a semiconductor device structure as claimed in claim 3 , further comprising: forming an isolation structure over the dummy fin structure, wherein the dummy fin structure is embedded in the isolation structure after removing the middle portion of the dummy fin structure. 5. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising: forming a hard mask layer over the dummy fin structure, wherein a portion of the hard mask layer is removed when the top portion of the dummy fin structure is removed. 6. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising: forming a fin structure over a substrate; forming the mask layer covering the fin structure; and removing a middle portion of the dummy fin structure without removing the fin structure, such that a top surface of the dummy fin structure is lower than a top surface of the fin structure after removing the middle portion of the dummy fin structure. 7. A method for forming a semiconductor device structure, comprising: forming a fin structure and a dummy fin structure; forming a hard mask layer over the fin structure and the dummy fin structure; forming a mask layer over the hard mask layer; and removing a portion of the mask layer, a portion of the hard mask layer and a top portion of the dummy fin structure, such that another portion of the hard mask layer remains on the dummy fin structure. 8. The method for forming a semiconductor device structure as claimed in claim 7 , wherein the dummy fin structure has a protruding portion which is directly below the another portion of the hard mask layer. 9. The method for forming a semiconductor device structure as claimed in claim 8 , further comprising: removing a middle portion of the dummy fin structure without removing the another portion of the hard mask layer. 10. The method for forming a semiconductor device structure as claimed in claim 9 , wherein a top surface of the dummy fin structure is lower than a top surface of the fin structure after removing the middle portion of the dummy fin structure. 11. The method for forming a semiconductor device structure as claimed in claim 10 , further comprising: forming an isolation structure over the dummy fin structure, wherein the dummy fin structure is embedded in the isolation structure after removing the middle portion of the dummy fin structure. 12. A method for forming a semiconductor device structure, comprising: forming a fin structure and a dummy fin structure; forming a mask layer covering the fin structure; and forming a concave or convex top surface on the dummy fin structure by removing a top portion of the dummy fin structure, wherein the concave top surface has a smooth top surface that curves inwards, or the convex top surface has a smooth top surface that curves outwards. 13. The method for forming a semiconductor device structure as claimed in claim 12 , further comprising: irradiating the mask layer, so that the mask layer is divided into an unirradiated portion and an irradiated portion, wherein the unirradiated portion is over the fin structure. 14. The method for forming a semiconductor device structure as claimed in claim 13 , wherein a first sidewall of the dummy fin structure is in direct contact with the unirradiated portion, and a second sidewall of the dummy fin structure is in direct contact with the irradiated portion. 15. The method for forming a semiconductor device structure as claimed in claim 12 , further comprising: forming a hard mask layer over the fin structure, wherein the hard mask layer is not removed when the top portion of the dummy fin structure is removed. 16. The method for forming a semiconductor device structure as claimed in claim 12 , wherein a center of the dummy fin structure is etched slower than sidewalls of the dummy fin structure during removing the top portion of the dummy fin structure. 17. The method for forming a semiconductor device structure as claimed in claim 12 , further comprising: forming an asymmetric dummy fin structure adjacent to the fin structure, wherein a protruding portion of the asymmetric dummy fin structure is higher than a top surface of the dummy fin structure. 18. The method for forming a semiconductor device structure as claimed in claim 17 , further comprising: forming a hard mask layer over the protruding portion of the asymmetric dummy fin structure. 19. The method for forming a semiconductor device structure as claimed in claim 12 , wherein an entire top surface of the concave or convex top surface continuously extends from a left sidewall of the mask layer to a right sidewall of the mask layer. 20. The method for forming a semiconductor device structure as claimed in claim 12 , further comprising: forming an isolation feature, wherein the step of forming the isolation feature is after the step of forming the smooth top surface of the concave top surface or the smooth top surface of the convex top surface.

Assignees

Inventors

Classifications

  • of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

  • formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

  • having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

  • the components including FinFETs · CPC title

  • using silicon technology, e.g. SiGe · CPC title

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What does patent US11081571B2 cover?
Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure, and forming a mask layer covering the dummy fin structure. The method also includes removing a portion of the mask layer and a top portion of the dummy fin structure by a first etching operation to form an etched mask layer, wherein the dummy fin structure has a …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D84/0158. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 03 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).