Fin field effect transistors and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2016197075-A1
Application number	US-201514975917-A
Country	US
Kind code	A1
Filing date	Dec 21, 2015
Priority date	Jan 6, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

A method for forming FinFETs includes providing a semiconductor substrate having at least a first fin in a first region and at least a second fin in a second region, and a first gate structure over the first fin and a second gate structure over the second fin; forming a first stress layer on the first fin and a first cover layer on the first stress layer; forming a second stress layer on the second fin and a second cover layer on the second stress layer; performing a first potential barrier reducing ion implantation process on the first cover layer; performing a second potential barrier reducing ion implantation process on the second cover layer; forming a first metal layer and a second metal layer; and forming a first contact layer on the first cover layer and a second contact layer on the second cover layer.

First claim

What is claimed is:

1 . A method for fabricating a semiconductor structure having a plurality of FinFETs, comprising:
providing a semiconductor substrate having a first region and a second region; forming at least a first fin on the semiconductor substrate in the first region and at least a second fin on the semiconductor substrate in the second region; forming a first gate structure over the first fin and a second gate structure over the second fin; forming a first stress layer on the first fin at both sides of the first gate structure and a first cover layer on the first stress layer; forming a second stress layer on the second fin at both sides of the second gate structure and a second cover layer on the second stress layer; performing a first potential barrier reducing ion implantation process on the first cover layer; performing a second potential barrier reducing ion implantation process on the second cover layer; and forming a first contact layer on the first cover layer and a second contact layer on the second cover layer.

2 . The method according to claim 1 , wherein forming the first contact layer and the second contact layer further includes:
forming a first metal layer on the first cover layer and a second metal layer on the second cover layer; performing a first thermal annealing process on the first metal layer to form the first contact layer; and performing a second thermal annealing process on the second metal layer to form the second contact layer.

3 . The method according to claim 1 , wherein:
the first region is a PMOS region; and the second region is an NMOS region.

4 . The method according to claim 1 , wherein:
doing ions of the first potential barrier reducing ion implantation process include at one of Al ions, Ga ions, B ions, BF 2 ion, Ge ions and In ions.

5 . The method according to claim 4 , wherein:
doping ions of the first potential barrier reducing ion implantation process include at least one of Al ions, Ga ions, B ions, BF 2 and In ions; a doping dosage of the first potential barrier reducing ion implantation process is greater than or equal to 1E13 atom/cm 2 , and smaller than or equal to 1E14 atom/cm 2 ; and an energy of the first potential barrier reducing ion implantation process is greater than or equal to 5 KeV, and smaller than or equal to 30 KeV.

6 . The method according to claim 1 , wherein:
doing ions of the second potential barrier reducing ion implantation process include at least one of S ions, Se ions, As ions, Sb ion and Ga ions.

7 . The method according to claim 6 , wherein:
doping ions of the second potential barrier reducing ion implantation process include at least one of S ions, Se ions, As ions, and Sb ions; a doping dosage of the second potential barrier reducing ion implantation process is greater than or equal to 1E13 atom/cm 2 , and smaller than or equal to 1E14 atom/cm 2 ; and an energy of the second potential barrier reducing ion implantation process is greater than or equal to 5 KeV, and smaller than or equal to 30 KeV.

8 . The method according to claim 1 , wherein:
doping ions of the first potential barrier reducing ion implantation process are identical to doping ions of the second potential barrier reducing ion implantation process; and the first potential barrier reducing ion implantation process and the second potential barrier reducing ion implantation process are performed simultaneously.

9 . The method according to claim 8 , wherein:
doing ions of the first potential barrier reducing ion implantation process and the second potential barrier reducing ion implantation process are Ge ions; a doping dosage of the Ge ions is greater than or equal to 1E13 atom/cm 2 , and smaller than or equal to 1E14 atom/cm 2 ; and an energy of the first potential barrier reducing ion implantation process and the second potential barrier reducing ion implantation process are greater than or equal to 5 KeV, and smaller than or equal to 30 KeV.

10 . The method according to claim 1 , wherein performing the first potential barrier reducing ion implantation process further comprises:
forming a first patterned photoresist layer covering the semiconductor substrate in the second region and exposing the first region; and performing the first potential barrier reducing ion implantation process using the first patterned photoresist layer as a mask.

11 . The method according to claim 1 , wherein performing the first potential barrier reducing ion implantation process further comprises:
performing a boron ion implantation process in the first cover layer and the first potential barrier reducing ion implantation process simultaneously.

12 . The method according to claim 11 , wherein:
a doping dosage of the boron ions is greater than a doping dosage of the first potential barrier reducing ions.

13 . The method according to claim 1 , wherein performing the second potential barrier reducing ion implantation process further comprises:
performing a phosphorus ion implantation process in the second cover layer and the second potential barrier reducing ion implantation process simultaneously.

14 . The method according to claim 13 , wherein:
a doping dosage of the phosphorous ions is greater than a doping dosage of the second potential barrier reducing ions.

15 . The method according to claim 1 , wherein:
the first cover layer and the second cover layer are made of Si; and the first metal layer and the second metal layer are made of Ni.

16 . A semiconductor structure having a plurality of FinFETs, comprising:
a semiconductor substrate having a first region and a second region, at least a first fin formed on the semiconductor substrate in the first region and at least a second fin formed on the semiconductor substrate in the second region; a first gate structure formed on the first fin and a second gate structure formed over the second fin; a first stress layer formed on the first fin at both sides of the first gate structure; a second stress layer formed on the second fin at both sides of the second gate structure; a first contact layer, of which a bottom interface has a first dipole layer, formed on the first stress layer; and a second contact layer, of which a bottom interface has a second dipole layer, formed on the second stress layer.

17 . The semiconductor structure according to claim 16 , wherein:
the first region is a PMOS region; the second region is an NMOS region; the first stress layer is made of silicon germanium; and the second stress layer is made of silicon carbide.

18 . The semiconductor structure according to claim 16 , wherein:
the first contact layer and the second contact layer are metal silicide layers.

19 . The semiconductor structure according to claim 16 , wherein the first contact layer and the second contact layer are formed by:
forming a first cover layer on the first stress layer; forming a second cover layer on the second stress layer; performing a first potential barrier reducing ion implantation process on the first cover layer; performing a second potential barrier reducing ion implantation process on the second cover layer; forming a first metal layer on the first cover layer and a second metal layer on the second cover layer; performing a first thermal annealing process on the first metal layer to form the first contact layer; and performing a second thermal annealing process on the second metal layer to form the second contact layer.

Assignees

• Semiconductor Mfg Int Shanghai

Inventors

• Li Yong
• Wei Chengqing

Classifications

• H10P30/22

  using masks · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/834

  further characterised by the dopants · CPC title