High resistivity SOI wafers and a method of manufacturing thereof

Patent metadata

Field	Value
Publication number	US-11081386-B2
Application number	US-202016948376-A
Country	US
Kind code	B2
Filing date	Sep 16, 2020
Priority date	Jan 23, 2014
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.

First claim

What is claimed is:

1. A multilayer structure comprising:
a single crystal silicon wafer handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon wafer handle substrate and the other of which is a back surface of the single crystal silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon wafer handle substrate, and a central plane of the single crystal silicon wafer handle substrate between the front and back surfaces of the single crystal silicon wafer handle substrate, wherein the single crystal silicon wafer handle substrate comprises a p-type dopant and has a bulk resistivity between about 750 Ohm-cm and about 100,000 Ohm-cm;
an intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate, wherein the intermediate semiconductor layer is between the front surface of the single crystal silicon wafer handle substrate and a charge trapping layer and further wherein the intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprising a material selected from the group consisting of Si 1-x Ge x , Si 1-x C x , Si 1-x-y Ge x Sn y , Si 1-x-y-z Ge x Sn y C z , Ge 1-x Sn x , and any combination thereof wherein x, y, and z are molar ratios with values between 0.1 and 0.9, and further wherein the molar ratio of Ge in the intermediate semiconductor layer increases in the direction perpendicular from the single crystal silicon wafer handle substrate and toward the charge trapping layer;
the charge trapping layer between the intermediate semiconductor layer and a semiconductor oxide layer;
the semiconductor oxide layer in interfacial contact with the charge trapping layer; and
a single crystal silicon device layer in interfacial contact with the semiconductor oxide layer.

2. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has <100> crystal orientation.

3. The multilayer structure of claim 1 wherein the front surface of the single crystal silicon wafer handle substrate is oxidized.

4. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 1000 ohm cm and about 10,000 Ohm-cm.

5. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 2000 Ohm cm and about 10,000 Ohm-cm.

6. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm cm and about 5,000 Ohm-cm.

7. The multilayer structure of claim 1 wherein the intermediate semiconductor layer comprises a strained intermediate semiconductor layer.

8. The multilayer structure of claim 1 wherein the intermediate semiconductor layer comprises a partially relaxed intermediate semiconductor layer.

9. The multilayer structure of claim 1 wherein the intermediate semiconductor layer comprises a fully relaxed intermediate semiconductor layer.

10. The multilayer structure of claim 1 wherein the intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate comprises an amorphous structure and comprises Si 1-x Ge x , wherein the value of x is between 0.1 and 0.9.

11. The multilayer structure of claim 1 wherein the intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate comprises an amorphous structure and comprises Si 1-x Ge, wherein the value of x is between 0.2 and 0.7.

12. A multilayer structure comprising:
a single crystal silicon wafer handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon wafer handle substrate and the other of which is a back surface of the single crystal silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon wafer handle substrate, and a central plane of the single crystal silicon wafer handle substrate between the front and back surfaces of the single crystal silicon wafer handle substrate, wherein the single crystal silicon wafer handle substrate comprises a p-type dopant and has a bulk resistivity between about 750 Ohm-cm and about 100,000 Ohm-cm;
a charge trapping layer between the front surface of the single crystal silicon wafer handle substrate and an intermediate semiconductor layer;
the intermediate semiconductor layer, wherein the intermediate semiconductor layer has electron affinity lower than that of the single crystal silicon wafer handle substrate, wherein the intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprising a material selected from the group consisting of Si 1-x Ge x , Si 1-x C x , Si 1-x-y Ge x Sn y , Si 1-x-y-z Ge x Sn y C z , Ge 1-x Sn x , and any combination thereof wherein x, y, and z are molar ratios with values between 0.1 and 0.9, and further wherein the molar ratio of Ge in the intermediate semiconductor layer increases in the direction perpendicular from the single crystal silicon wafer handle substrate and toward a semiconductor oxide layer;
the semiconductor oxide layer in interfacial contact with the intermediate semiconductor layer; and
a single crystal silicon device layer in interfacial contact with the semiconductor oxide layer.

13. The multilayer structure of claim 12 wherein the single crystal silicon wafer handle substrate has <100> crystal orientation.

14. The multilayer structure of claim 12 wherein the front surface of the single crystal silicon wafer handle substrate is oxidized.

15. The multilayer structure of claim 12 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 1000 ohm cm and about 10,000 Ohm-cm.

16. The multilayer structure of claim 12 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 2000 Ohm cm and about 10,000 Ohm-cm.

17. The multilayer structure of claim 12 wherein the single crystal silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm cm and about 5,000 Ohm-cm.

18. The multilayer structure of claim 12 wherein the intermediate semiconductor layer comprises a strained intermediate semiconductor layer.

19. The multilayer structure of claim 12 wherein the intermediate semiconductor layer comprises a partially relaxed intermediate semiconductor layer.

20. The multilayer structure of claim 12 wherein the intermediate semiconductor layer comprises a fully relaxed intermediate semiconductor layer.

21. The multilayer structure of claim 12 wherein the intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate comprises an amorphous structure and comprises Si 1-x Ge x , wherein the value of x is between 0.1 and 0.9.

22. The multilayer structure of claim 12 wherein the intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate comprises an amorphous structure and comprises Si 1-x Ge, wherein the value of x is between 0.2 and 0.7.

Assignees

• Globalwafers Co Ltd

Inventors

• Peidous Igor
• Kommu Srikanth
• Wang Gang
• Thomas Shawn George

Classifications

• H10P90/1918

  including charge trapping layers, e.g. polycrystalline materials · CPC title

• H10P90/1916 Primary

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914 Primary

  using bonding · CPC title

• H01L21/76251 Primary

  Electricity · mapped topic